公开(公告)号：US20030011049A1

公开(公告)日：2003-01-16

申请号：US09904306

申请日：2001-07-12

Applicant: Custom One Design, Inc.

Inventor： Peter R. Nuytkens ,  Ilya E. Popeko ,  Joseph M. Kulinets

IPC: H01L023/495

CPC classification number: H01L21/4846 ,  C23C18/1653 ,  C23C18/1858 ,  C23C18/1879 ,  C23C18/2006 ,  C23C18/202 ,  C23C18/206 ,  C23C18/22 ,  C23C18/285 ,  C23C18/30 ,  H01L21/4864 ,  H01L21/6835 ,  H01L21/76873 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/181 ,  H01L2924/00

Abstract: A method for plating metal on a dielectric material includes dipping the dielectric in a solution containing catalytic metal particles. These particles have a dipole which helps them attach to the dielectric's surface. The dielectric's surface can be roughened to make it more attractive to such particles. The dielectric material is then placed in a metal salt solution that causes metal to be plated upon the dielectric by electroless plating. A thicker metallic layer can be deposited on top of the resulting layer by electroplating. This or other methods can be used to make an electrical circuit having one or more dielectric layers comprised of latex and one or more layers of conductive leads. A multichip module can be made which includes a plurality of integrated circuits mounted on a substrate; one or more dielectric layers comprised of a flexible dielectric material; and one or more layers of electrically conductive material patterned to interconnect such ICs. Such a module can be manufactured by placing a frame, with holes for holding integrated circuits, against a flat substrate. Integrated circuit chips are placed through the frame's holes to planarize their top surfaces against the flat substrate. The flat substrate is removed. One or more layers of dielectric are placed on top of the frames and chips. Photolithographic techniques are used to create conductive paths on the dielectric material between the ICs. The multichip module can also be manufactured by a similar process that does not use such frames.

Abstract translation: 在电介质材料上电镀金属的方法包括将电介质浸入含有催化金属颗粒的溶液中。 这些颗粒具有偶极子，有助于它们附着到电介质的表面。 电介质的表面可以被粗糙化以使其对这种颗粒更具吸引力。 然后将电介质材料置于金属盐溶液中，使金属通过化学镀被电镀在电介质上。 可以通过电镀将较厚的金属层沉积在所得层的顶部上。 这种或其它方法可以用于制造具有由胶乳和一层或多层导电引线组成的一个或多个介电层的电路。 可以制造多芯片模块，其包括安装在基板上的多个集成电路; 由柔性电介质材料构成的一个或多个电介质层; 以及图案化以互连这种IC的一层或多层导电材料。 这样的模块可以通过将具有用于保持集成电路的孔的框架放置在平坦的基板上来制造。 集成电路芯片通过框架的孔放置，使其顶表面平坦化平坦的基板。 去除平坦的基底。 将一层或多层电介质放置在框架和芯片的顶部。 光刻技术用于在IC之间的电介质材料上形成导电路径。 多芯片模块也可以通过不使用这种框架的类似工艺来制造。

公开(公告)号：US20030011458A1

公开(公告)日：2003-01-16

申请号：US09904014

申请日：2001-07-12

Applicant: Custom One Design, Inc.

Inventor： Peter R. Nuytkens ,  Ilya E. Popeko ,  Joseph M. Kulinets

IPC: H01F005/00

CPC classification number: H05K1/165 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/24 ,  H01F27/2804 ,  H01F27/365 ,  H01F41/02 ,  H01F41/046 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/15153 ,  H05K3/184 ,  H05K3/381 ,  H05K3/4614 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2203/072 ,  Y10T29/4902 ,  Y10T29/49073 ,  Y10T29/49075 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: A printed circuit board has two layers of printed circuit board dielectric material; a core made of ferromagnetic material between the two layers; and conductive leads on the opposite side of each dielectric layer from the core connected by via holes through both dielectric layers to form a conducting coil around the core. The conductive leads can form two separate coils around the core to form a transformer. A planar conducing sheet can be placed on or between one or more of the printed circuit board's dielectric layers to shield other circuitry on the printed circuit board from magnetic fields generated around the core. The core can be formed at least in part by electroless plating. Electroplating can be used to add a thicker layer of less conductive ferromagnetic material. Ferromagnetic inductive cores can be formed on the surface of a dielectric material by: dipping the surface of the dielectric in a solution containing catalytic metal particles having a slight dipole; and placing the dielectric in a metal salt to cause a layer containing metal to be electrolessly plated upon the dielectric. Plasma etching or other technique can be used before the dipping process to roughen the dielectric's surface to help attract the catalytic particles. This method can be used to form an inductor core on or between one or more dielectric layers of a printed circuit board, of a multichip module, of an integrated circuit, or of a micro-electromechanical device.

Abstract translation: 印刷电路板具有两层印刷电路板电介质材料; 由两层之间的铁磁材料制成的铁芯; 并且每个电介质层的相对侧上的导电引线与通过两个电介质层的通孔连接的芯体形成围绕芯的导电线圈。 导电引线可以在芯周围形成两个分离的线圈以形成变压器。 平面导电片可以放置在印刷电路板的介电层中的一个或多个之上或之上，以屏蔽印刷电路板上的其它电路与芯周围产生的磁场。 芯可以至少部分地通过无电镀形成。 可以使用电镀来增加较薄的较不导电的铁磁材料层。 可以通过以下步骤在电介质材料的表面上形成铁磁感应芯：将电介质的表面浸入含有具有轻微偶极子的催化金属颗粒的溶液中; 并将电介质放置在金属盐中以使含有金属的层无电镀在电介质上。 在浸渍过程之前可以使用等离子体蚀刻或其它技术来粗糙化电介质的表面以帮助吸引催化剂颗粒。 该方法可以用于在印刷电路板，多芯片模块，集成电路或微机电装置的一个或多个电介质层之间或之上形成电感器芯。