公开(公告)号：US20060219573A1

公开(公告)日：2006-10-05

申请号：US11445594

申请日：2006-06-01

Applicant: Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Douglas Young

Inventor： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Douglas Young

IPC: B23H3/00

CPC classification number: B24B37/20 ,  B24B37/046 ,  B24B37/24 ,  B24B37/26 ,  C25D5/06 ,  C25D17/001 ,  C25D17/14 ,  C25F7/00 ,  H01L21/2885 ,  H01L21/76877

Abstract: The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.

Abstract translation: 本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。 这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。 在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上， 在工件和阳极之间施加电位差。 在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。 在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

公开(公告)号：US20060070885A1

公开(公告)日：2006-04-06

申请号：US11295014

申请日：2005-12-06

Applicant: Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol

Inventor： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol

IPC: C25D5/02 ,  C25D5/48

CPC classification number: C25D5/00 ,  C23C18/1608 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1848 ,  C23C18/31 ,  C25D5/02 ,  C25D5/10 ,  C25D5/22 ,  C25D5/34 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76885 ,  H01L24/11 ,  H01L2221/1089 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3011

Abstract: The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

公开(公告)号：US06974769B2

公开(公告)日：2005-12-13

申请号：US10663318

申请日：2003-09-16

Applicant: Bulent Basol ,  Homayoun Talieh ,  Cyprian Uzoh

Inventor： Bulent Basol ,  Homayoun Talieh ,  Cyprian Uzoh

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/7684

Abstract: Conductive structures in features of an insulator layer on a substrate are fabricated by a particular process. In this process, a layer of conductive material is applied over the insulator layer so that the layer of conductive material covers field regions adjacent the features and fills in the features themselves. A grain size differential between the conductive material which covers the field regions and the conductive material which fills in the features is then established by annealing the layer of conductive material. Excess conductive material is then removed to uncover the field regions and leave the conductive structures. The layer of conductive material is applied so as to define a first layer thickness over the field regions and a second layer thickness in and over the features. These thicknesses are dimensioned such that d1≦0.5d2, with d1 being the first layer thickness and d2 being the second layer thickness. Preferably, the first and second layer thicknesses are dimensioned such that d1≦0.3d2.

Abstract translation: 通过特定的工艺制造衬底上的绝缘体层的特征的导电结构。 在该过程中，将导电材料层施加在绝缘体层上，使得导电材料层覆盖与特征相邻的场区域并填充特征本身。 然后通过退火导电材料层来建立覆盖场区的导电材料与填充特征的导电材料之间的晶粒尺寸差。 然后去除过量的导电材料以露出场区并留下导电结构。 施加导电材料层以在场区域上限定第一层厚度，并且在特征中和之上限定第二层厚度。 这些厚度的尺寸使得其中d 1是第一层厚度，d 2 <2 < / SUB>为第二层厚度。 优选地，第一层厚度和第二层厚度的尺寸被确定为使得d 1 = 0.3D 2。

公开(公告)号：US20050029123A1

公开(公告)日：2005-02-10

申请号：US10637731

申请日：2003-08-08

Applicant: Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Halit Yakupoglu

Inventor： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Halit Yakupoglu

IPC: H01L21/321 ,  B29C71/02 ,  B05D5/12

CPC classification number: H01L21/32125

Abstract: The methods and systems described provide for radiation assisted material deposition, removal, and planarization at a surface, edge, and/or bevel of a workpiece such as a semiconductor wafer. Exemplary processes performed on a workpiece surface having topographical features include radiation assisted electrochemical material deposition, which produces an adsorbate layer outside of the features to suppress deposition outside of the features and to encourage, through charge conservation, deposition into the features to achieve, for example, a planar surface profile. A further exemplary process is radiation assisted electrochemical removal of material, which produces an adsorbate layer in the features to suppress removal of material from the features and to encourage, through charge conservation, removal of material outside of the features so that, for example, a planar surface profile is achieved.

Abstract translation: 所描述的方法和系统提供了诸如半导体晶片的工件的表面，边缘和/或斜面处的辐射辅助材料沉积，去除和平坦化。 在具有形貌特征的工件表面上执行的示例性工艺包括辐射辅助电化学材料沉积，其在特征之外产生吸附物层以抑制特征外的沉积，并且通过电荷保存沉积到特征中以实现例如 ，平面表面轮廓。 进一步的示例性方法是材料的辐射辅助电化学去除，其在特征中产生吸附物层以抑制材料从特征中的去除并且通过电荷保持除去特征外的材料，从而例如， 实现了平面表面轮廓。

公开(公告)号：US07378004B2

公开(公告)日：2008-05-27

申请号：US10152793

申请日：2002-05-23

Applicant: Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

Inventor： Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

IPC: B24D11/00 ,  C25D5/22 ,  C25F3/00 ,  H01L21/3063

CPC classification number: B24B37/26 ,  B23H5/08 ,  C25D17/001 ,  C25D17/14

Abstract: An apparatus capable of assisting in controlling an electrolyte flow and an electric field distribution used for processing a substrate is provided. It includes a rigid member having a top surface of a predetermined shape and a bottom surface. The rigid member contains a plurality of channels, each forming a passage from the top surface to the bottom surface, and each allowing the electrolyte and electric field flow therethrough. A pad is attached to the rigid member via a fastener. The pad also allows for electrolyte and electric field flow therethrough to the substrate.

Abstract translation: 提供一种能够辅助控制用于处理基板的电解质流动和电场分布的装置。 它包括具有预定形状的顶表面和底表面的刚性构件。 刚性构件包括多个通道，每个通道形成从顶表面到底表面的通道，并且每个通道允许电解质和电场流过其中。 垫通过紧固件附接到刚性构件。 衬垫还允许电解质和电场流过衬底。

公开(公告)号：US20060118425A1

公开(公告)日：2006-06-08

申请号：US11343477

申请日：2006-01-30

Applicant: Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: C25D5/02

CPC classification number: C25D5/022 ,  C25D5/18 ,  C25D5/22 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76877

Abstract: A layer structure usable in manufacturing an integrated circuit is made, in a single apparatus, by a particular process in which a patterned substrate is provided. An electrolyte solution, out of which a conductive material can be plated under an applied potential, is supplied over a surface of the patterned substrate, and a potential is applied so as to deposit a film of the conductive material out of the electrolyte solution and over the surface of the patterned substrate. The film of conductive material is preferably polished as it is deposited. The conductive material is then removed from field regions of the patterned substrate, while deposits of the conductive material are left in features defined in the patterned substrate. The deposits of the conductive material are then electrically isolated, resulting in the layer structure.

Abstract translation: 在单一设备中，通过提供图案化衬底的特定工艺制造可用于制造集成电路的层结构。 在图案化衬底的表面上提供电解质溶液，其中可以在施加电位下电镀导电材料，并且施加电位以将导电材料的膜从电解质溶液中沉积出来并且越过 图案化衬底的表面。 导电材料的膜优选在其沉积时被抛光。 导电材料然后从图案化衬底的场区域移除，而导电材料的沉积物留在图案化衬底中限定的特征中。 然后导电材料的沉积物被电隔离，导致层结构。

公开(公告)号：US20050095854A1

公开(公告)日：2005-05-05

申请号：US10698878

申请日：2003-10-31

Applicant: Cyprian Uzoh ,  Bulent Basol

Inventor： Cyprian Uzoh ,  Bulent Basol

IPC: H01L21/288 ,  H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76877 ,  H01L21/2885

Abstract: A process of electrodepositing a substantially flat conductive layer on a workpiece surface is provided. In the process, various transition current densities are determined experimentally by evaluating the effects of the plating current density on gap fill profile in the smallest cavities with the largest tendency to over-plate on the substrate. After determining the transition currents on experimental wafers or dies, an electrochemical plating process is performed to apply selected transition current densities as process current densities to form a substantially flat profile over the smallest cavities.

Abstract translation: 提供了在工件表面上电沉积基本平坦的导电层的工艺。 在此过程中，通过评估电镀电流密度对最小空腔中的间隙填充轮廓的影响，在基板上具有最大的过平板倾向，实验确定了各种转变电流密度。 在确定实验晶片或裸片上的转换电流之后，执行电化学电镀工艺以将所选择的过渡电流密度用作过程电流密度，以在最小空腔上形成基本平坦的轮廓。

公开(公告)号：US20050079713A1

公开(公告)日：2005-04-14

申请号：US10920028

申请日：2004-08-16

Applicant: Jalal Ashjaee ,  Rimma Volodarsky ,  Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

Inventor： Jalal Ashjaee ,  Rimma Volodarsky ,  Cyprian Uzoh ,  Bulent Basol ,  Homayoun Talieh

IPC: H01L21/00 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/6708 ,  H01L21/2885 ,  H01L21/32134

Abstract: The present invention provides at least one nozzle that sprays a rotating workpiece with an etchant at an edge thereof. The at least one nozzle is located in an upper chamber of a vertically configured processing subsystem that also includes mechanisms for plating, cleaning and drying in upper and lower chambers

Abstract translation: 本发明提供了至少一个喷嘴，其在其边缘处用蚀刻剂喷射旋转的工件。 所述至少一个喷嘴位于垂直构造的处理子系统的上腔室中，所述处理子系统还包括用于在上腔室和下室中进行电镀，清洁和干燥的机构

公开(公告)号：US20060011485A1

公开(公告)日：2006-01-19

申请号：US11232026

申请日：2005-09-20

Applicant: Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Bulent Basol ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: C25D5/10 ,  C25D5/02

CPC classification number: C25D5/02 ,  C25D5/22 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76877

Abstract: The present invention relates to a method for forming a planar conductive surface on a wafer. In one aspect, the present invention uses a no-contact process with electrochemical deposition, followed by a contact process with electrochemical mechanical deposition.

公开(公告)号：US20050145489A1

公开(公告)日：2005-07-07

申请号：US11054053

申请日：2005-02-08

Applicant: Bulent Basol ,  Cyprian Uzoh ,  Halit Yakupoglu ,  Homayoun Talieh

Inventor： Bulent Basol ,  Cyprian Uzoh ,  Halit Yakupoglu ,  Homayoun Talieh

IPC: B23H5/08 ,  C25F3/14 ,  H01L21/288 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  C25B9/00 ,  C25D17/00

CPC classification number: H01L21/32115 ,  B23H5/08 ,  C25F3/14 ,  H01L21/2885 ,  H01L21/32134 ,  H01L21/7684

Abstract: A system for optionally depositing or etching a layer of a wafer includes mask plate opposed to the wafer with the mask plate having a plurality of openings that transport a solution to the wafer. An electrode assembly has a first electrode member and a second electrode member having channels that operatively interface a peripheral and center part of the wafer. The channels transport the solution to the mask.