Bus interface controller for serially-accessed variable-access-time
memory device
    1.
    发明授权
    Bus interface controller for serially-accessed variable-access-time memory device 失效
    总线接口控制器,用于串行访问可变存取时存储器件

    公开(公告)号:US5901293A

    公开(公告)日:1999-05-04

    申请号:US669942

    申请日:1996-06-25

    CPC classification number: G06F13/4239

    Abstract: A method and controller circuitry for coupling a variable access time serial memory device to a microprocessor is disclosed. The controller circuitry includes an input for receiving address signal lines and control signal lines generated by the microprocessor, control signal lines generated by the device, and control signal lines and data signal lines for sending signals to the microprocessor and to the device. The controller circuitry further includes a decoder, responsive to the received address signal lines and control signal lines, for determining if the device can immediately respond to the microprocessor-generated request. If the device can respond to the request immediately the controller circuitry signals the device to respond to the request; otherwise, the controller circuitry responds to the request, and sends signals to the device to prepare the device to respond to future microprocessor-generated requests. The controller circuitry further includes memory to allow it to alter its responses to the microprocessor and its signals to the device dependent upon prior signals it has sent and received.

    Abstract translation: 公开了一种用于将可变存取时间串行存储器件耦合到微处理器的方法和控制器电路。 控制器电路包括用于接收由微处理器产生的地址信号线和控制信号线的输入,由该器件产生的控制信号线,以及用于向微处理器和设备发送信号的控制信号线和数据信号线。 控制器电路还包括响应于接收到的地址信号线和控制信号线的解码器,用于确定设备是否可以立即响应微处理器产生的请求。 如果设备可以立即响应请求,则控制器电路发信号通知设备以响应请求; 否则,控制器电路响应该请求,并向该设备发送信号以准备该设备以响应将来的微处理器产生的请求。 控制器电路还包括存储器,以允许其根据已经发送和接收的先前信号来改变其对微处理器的响应及其对设备的信号。

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