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公开(公告)号：US6156484A
公开(公告)日：2000-12-05
申请号：US21758
申请日：1998-02-11
Applicant: Ernest Bassous , Gobinda Das , Frank Daniel Egitto , Natalie Barbara Feilchenfeld , Elizabeth F. Foster , Stephen Joseph Fuerniss , James Steven Kamperman , Donald Joseph Mikalsen , Michael Roy Scheuermann , David Brian Stone
Inventor： Ernest Bassous , Gobinda Das , Frank Daniel Egitto , Natalie Barbara Feilchenfeld , Elizabeth F. Foster , Stephen Joseph Fuerniss , James Steven Kamperman , Donald Joseph Mikalsen , Michael Roy Scheuermann , David Brian Stone
CPC classification number: G01R1/06738 , G01R1/07314 , G01R3/00
Abstract: Disclosed is a sculpted probe pad and a gray scale etching process for making arrays of such probe pads on a thin flexible interposer for testing the electrical integrity of microelectronic devices at terminal metallurgy. Also used in the etching process is a novel fixture for holding the substrate and a novel mask for 1-step photolithographic exposure. The result of the invention is an array of test probes of preselected uniform topography, which make ohmic contact at all points to be tested simultaneously and nondestructively.
Abstract translation: 公开了一种雕刻的探针焊盘和灰度蚀刻工艺，用于在薄的柔性插入件上制造这种探针焊盘的阵列，用于测试终端冶金时的微电子器件的电气完整性。 用于蚀刻工艺中的还有一种用于保持衬底的新型夹具和用于1步光刻曝光的新型掩模。 本发明的结果是预选的均匀地形的测试探针的阵列，其在所有点上进行欧姆接触以同时且非破坏性地测试。
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公开(公告)号：US5669775A
公开(公告)日：1997-09-23
申请号：US524361
申请日：1995-09-05
Applicant: Jeffrey Scott Campbell , James D. Herard , Ronald Peter Nowak , John Robert Slack , David Brian Stone
Inventor： Jeffrey Scott Campbell , James D. Herard , Ronald Peter Nowak , John Robert Slack , David Brian Stone
CPC classification number: H01R23/661 , H05K1/189 , H05K1/117 , H05K1/118 , H05K2201/10189 , H05K2201/10424 , H05K2201/2009 , H05K3/0058
Abstract: A support structure is attached to the front or back side of a flexible circuit by direct mounting to the flexible circuit flat ribbon cable, thereby providing a stress-free region of the cable in which the flexible circuit electrical components can be mounted. The support structure comprises a flat ring that is attached to the cable by adhesive, soldering, or mechanical fastening. The flat ring mounts on one side of the flat ribbon cable and encloses an area of the cable that is sufficiently large for the mounting of the flexible circuit electrical components. The flat ribbon cable within the enclosed area is held flat and free from stress, even as the cable is handled. Thus, any components mounted within the enclosed area are not subjected to bending moments. The invention also can be incorporated into cable connectors, such as multi-pin connectors at the ends of cables, and can include support hooks and air cooling baffles.
Abstract translation: 支撑结构通过直接安装到柔性电路扁平带状电缆而附接到柔性电路的前侧或后侧，由此提供电缆的无应力区域，其中可安装柔性电路电气部件。 支撑结构包括通过粘合剂，焊接或机械紧固附接到电缆的平环。 扁平环安装在扁平带状电缆的一侧，并且包围电缆的足够大的区域以用于安装柔性电路电气部件。 封闭区域内的扁平带状电缆保持平坦，无应力，即使电缆处理。 因此，安装在封闭区域内的任何部件都不会受到弯矩的影响。 本发明还可以结合到电缆连接器中，例如在电缆端部处的多针连接器，并且可以包括支撑钩和空气冷却挡板。
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公开(公告)号：US5920037A
公开(公告)日：1999-07-06
申请号：US855812
申请日：1997-05-12
Applicant: Lisa Jeanine Jimarez , David Noel Light , Andrew Michael Seman , David Brian Stone
Inventor： Lisa Jeanine Jimarez , David Noel Light , Andrew Michael Seman , David Brian Stone
CPC classification number: H05K3/0061 , H05K3/321 , H05K3/382 , H05K1/111 , H05K2203/025 , H05K2203/0307 , H05K2203/0315 , H05K2203/1105 , Y10T29/49144 , Y10T29/49155
Abstract: The present invention provides a new device and technique for enhancing the electrical properties of the thick metal backer/adhesive bond/ground plane interface. The enhanced electrical properties are obtained by micro-roughening a connection surface of the thick metal backer prior to forming the thick metal backer/adhesive bond/ground plane interface.
Abstract translation: 本发明提供了一种用于增强厚金属衬底/粘合剂接合/接地平面界面的电性能的新型装置和技术。 通过在形成厚金属衬垫/粘合剂接合/接地平面界面之前，通过对粗金属衬底的连接表面进行微粗化来获得增强的电性能。
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公开(公告)号：US5759046A
公开(公告)日：1998-06-02
申请号：US773922
申请日：1996-12-30
Applicant: Anthony Paul Ingraham , Jaynal Abedin Molla , David Brian Stone
Inventor： Anthony Paul Ingraham , Jaynal Abedin Molla , David Brian Stone
Abstract: A technique of connecting a first member having a first face to a second member having a second face utilizing dendrites is provided. Dendrites are formed on one face of the first member in a given configuration. Dendrite receiving and securing material, preferably solder, is formed on a face of the second member in a configuration confirming substantially to the given configuration of the dendrites on the one face. The first and second members are then placed in a position relative to each other with the dendrites on the one face of the first member in contact with the dendrite receiving and engaging material on the face of the second member. An airtight seal is then provided between the first and second faces surrounding the dendrites and dendrite receiving and engaging material, which forms a sealed chamber between the first and second members. Thereafter, a vacuum is pulled within the sealed chamber, thereby causing the ambient air pressure on the two members to urge the two members toward each other which will embed the dendrites in the dendrite receiving and engaging material to form interconnection therebetween. In order to enhance or improve the bond between the dendrites and the dendrite receiving and securing material, the dendrites and dendrite receiving and securing material each contain a component which can form an intermetallic compound therebetween.
Abstract translation: 提供了一种将具有第一面的第一构件与具有第二面的第二构件连接起来利用枝晶的技术。 在给定的构造中，树枝状体形成在第一构件的一个面上。 树枝状接收和固定材料（优选焊料）形成在第二构件的表面上，其构造基本上确认了在一个面上的树突的给定构型。 然后将第一和第二构件相对于彼此放置在第一构件的一个面上的树突与第二构件的表面上的枝晶接收和接合材料接触的位置。 然后在围绕树突和树枝状晶体接收和接合材料的第一和第二表面之间提供气密密封，其在第一和第二构件之间形成密封室。 此后，在密封室内拉动真空，从而使两个构件上的环境空气压力相互推动两个构件，这两个构件将将树枝状物嵌入枝晶接收和接合材料中以在其间形成互连。 为了增强或改善枝晶与树枝状晶体接收和固定材料之间的结合，枝晶和枝晶接收和固定材料各自含有可在其间形成金属间化合物的组分。
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5.发明授权Cap providing flat surface for DCA and solder ball attach and for sealing plated through holes, multi-layer electronic sturctures including the cap 失效盖为DCA和焊球附着提供平坦表面，并用于密封电镀通孔，包括盖的多层电子结构
公开(公告)号：US5734560A
公开(公告)日：1998-03-31
申请号：US619096
申请日：1996-03-20
Applicant: James Steven Kamperman , Thomas Patrick Gall , David Brian Stone
Inventor： James Steven Kamperman , Thomas Patrick Gall , David Brian Stone
IPC: H01L21/48 , H01L23/498 , H01L23/538 , H05K1/11 , H05K3/00 , H05K3/06 , H05K3/20 , H05K3/34 , H05K3/40 , H05K3/46 , H01R9/00
CPC classification number: H01L23/49827 , H01L21/486 , H01L23/49833 , H01L23/5384 , H01L23/5385 , H05K1/113 , H05K3/0094 , H05K3/4015 , H01L2224/16225 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15313 , H05K2201/096 , H05K2201/10734 , H05K2203/1394 , H05K3/062 , H05K3/064 , H05K3/205 , H05K3/3452 , H05K3/4614 , Y10T29/49126 , Y10T29/4913 , Y10T29/49142 , Y10T29/49144 , Y10T29/49149
Abstract: A cap for attaching a chip or other device to a multi-layer electronic structure. The cap includes a plurality of pads of an electrically-conducting material attached over plated through holes of the multi-layer electronic structure. Each of the pads includes a flat upper surface for attaching the chip or other device to the multi-layer structure, provides an electrical connection between the chip or other device and the multi-layer structure, and seals the through holes to prevent solder from entering the plated through hole. The pads are physically isolated from each other.
Abstract translation: 用于将芯片或其他设备附接到多层电子结构的盖。 盖包括多个电导材料的焊盘，附着在多层电子结构的电镀通孔上。 每个焊盘包括用于将芯片或其他器件附接到多层结构的平坦的上表面，在芯片或其他器件与多层结构之间提供电连接，并且密封通孔以防止焊料进入 电镀通孔。 垫片彼此物理隔离。
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Patent Agency Ranking
公开(公告)号：US07765509B2
公开(公告)日：2010-07-27
申请号：US11858995
申请日：2007-09-21
Applicant: Adam Matthew Bittner , Timothy W. Budell , Robert C. Cusimano , Richard Dauphin , Matthew Thomas Guzowski , Craig Paul Lussier , David Brian Stone , Patrick G. Wilder
Inventor： Adam Matthew Bittner , Timothy W. Budell , Robert C. Cusimano , Richard Dauphin , Matthew Thomas Guzowski , Craig Paul Lussier , David Brian Stone , Patrick G. Wilder
IPC: G06F17/50
CPC classification number: H01L23/50 , G06F17/5077 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H01L2924/3011
Abstract: A system and method for generating simulated wiring connections between a semiconductor device and a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to the semiconductor device and identifying a plurality of second factors and instances of each second factor relating to the carrier. The first and second factors are associated with each other on a one-to-one basis. A simulated wiring connection is generated between a first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal. A simulated wiring connection is generated between third I/O terminals located in a first region and fourth I/O terminals located in a second region.
Abstract translation: 一种用于在半导体器件和载体之间产生模拟布线连接的系统和方法。 该方法包括识别与半导体器件相关的多个第一因子和每个第一因素的实例，并且识别与载波相关的每个第二因素的多个第二因素和实例。 第一和第二因素在一对一的基础上相互关联。 在第一I / O端子和匹配的第二I / O端子之间产生模拟的布线连接，受到每个第一I / O端子的每个第一因子的识别的实例与所识别的相关联的第二因子的实例相关联 匹配的第二个I / O终端。 在位于第一区域的第三I / O端子和位于第二区域中的第四I / O端子之间产生模拟布线连接。
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公开(公告)号：US06594891B1
公开(公告)日：2003-07-22
申请号：US09559654
申请日：2000-04-28
Applicant: James Steven Kamperman , Thomas Patrick Gall , David Brian Stone
Inventor： James Steven Kamperman , Thomas Patrick Gall , David Brian Stone
IPC: H05K330
CPC classification number: H01L23/49827 , H01L21/486 , H01L23/49833 , H01L23/5384 , H01L23/5385 , H01L2224/16225 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15313 , H05K1/113 , H05K3/0094 , H05K3/062 , H05K3/064 , H05K3/205 , H05K3/3452 , H05K3/4015 , H05K3/4614 , H05K2201/096 , H05K2201/10734 , H05K2203/1394 , Y10T29/49126 , Y10T29/4913 , Y10T29/49142 , Y10T29/49144 , Y10T29/49149
Abstract: A process of forming a multi-layer electronic composite structure. The process includes providing at least one core including at least one plane of at least one electrically conducting material with a plane of at least one electrically insulating material on both sides of the at least one plane of at least one electrically conducting material. The at least one core includes a plurality of placed through holes formed therethrough. At least one pad is provided over at least one of the plated through holes. The pad provides a flat surface for attaching an electronic device and also prevents solder from entering the at least one plated through hole.
Abstract translation: 一种形成多层电子复合结构的方法。 该方法包括提供至少一个芯，其包括至少一个导电材料的至少一个平面，其中至少一个导电材料的至少一个平面的两侧上具有至少一个电绝缘材料的平面。 所述至少一个芯包括穿过其形成的多个放置的通孔。 在至少一个电镀通孔上提供至少一个焊盘。 垫提供用于附接电子装置的平坦表面，并且还防止焊料进入至少一个电镀通孔。
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8.发明授权Process for forming multi-layer electronic structures including a cap for providing a flat surface for DCA and solder ball attach and for sealing plated through holes 失效用于形成多层电子结构的方法，包括用于提供用于DCA的平坦表面和焊球附着并用于密封电镀通孔的盖
公开(公告)号：US6098280A
公开(公告)日：2000-08-08
申请号：US3034
申请日：1998-01-05
Applicant: James Steven Kamperman , Thomas Patrick Gall , David Brian Stone
Inventor： James Steven Kamperman , Thomas Patrick Gall , David Brian Stone
IPC: H01L21/48 , H01L23/498 , H01L23/538 , H05K1/11 , H05K3/00 , H05K3/06 , H05K3/20 , H05K3/34 , H05K3/40 , H05K3/46 , H05K3/30
CPC classification number: H01L23/49827 , H01L21/486 , H01L23/49833 , H01L23/5384 , H01L23/5385 , H05K1/113 , H05K3/0094 , H05K3/4015 , H01L2224/16225 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15313 , H05K2201/096 , H05K2201/10734 , H05K2203/1394 , H05K3/062 , H05K3/064 , H05K3/205 , H05K3/3452 , H05K3/4614 , Y10T29/49126 , Y10T29/4913 , Y10T29/49142 , Y10T29/49144 , Y10T29/49149
Abstract: A process of forming a multi-layer electronic composite structure. The process includes providing at least one core including at least one plane of at least one electrically conducting material with a plane of at least one electrically insulating material on both sides of the at least one plane of at least one electrically conducting material. The at least one core includes a plurality of plated through holes formed therethrough. At least one pad is provided over at least one of the plated through holes. The pad provides a flat surface for attaching an electronic device and also prevents solder from entering the at least one plated through hole.
Abstract translation: 一种形成多层电子复合结构的方法。 该方法包括提供至少一个芯，其包括至少一个导电材料的至少一个平面，其中至少一个导电材料的至少一个平面的两侧上具有至少一个电绝缘材料的平面。 所述至少一个芯包括穿过其形成的多个电镀通孔。 在至少一个电镀通孔上提供至少一个焊盘。 垫提供用于附接电子装置的平坦表面，并且还防止焊料进入至少一个电镀通孔。
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公开(公告)号：US07275229B2
公开(公告)日：2007-09-25
申请号：US11159915
申请日：2005-06-23
Applicant: Adam Matthew Bittner , Timothy W. Budell , Robert C. Cusimano , Richard Dauphin , Matthew Thomas Guzowski , Craig Paul Lussier , David Brian Stone , Patrick G. Wilder
Inventor： Adam Matthew Bittner , Timothy W. Budell , Robert C. Cusimano , Richard Dauphin , Matthew Thomas Guzowski , Craig Paul Lussier , David Brian Stone , Patrick G. Wilder
IPC: G06F17/50
CPC classification number: H01L23/50 , G06F17/5077 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H01L2924/3011
Abstract: A system and method for generating simulated wiring connections between first I/O terminals of a semiconductor device and second I/O terminals of a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to a semiconductor device and identifying a plurality of second factors and instances of each second factor relating to a carrier. The first and second factors are associated with each other on a one-to-one basis. The instances of each first factor are correlated to the instances of each associated second factor on a one-to-one basis. A simulated wiring connection automatically is generated between each first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal.
Abstract translation: 一种用于在半导体器件的第一I / O端子与载体的第二I / O端子之间产生模拟布线连接的系统和方法。 该方法包括识别与半导体器件相关的每个第一因素的多个第一因素和实例，并且识别与载波相关的每个第二因素的多个第二因素和实例。 第一和第二因素在一对一的基础上相互关联。 每个第一因子的实例与每个相关联的第二因子的实例在一对一的基础上相关。 在每个第一I / O终端和匹配的第二I / O终端之间自动生成模拟接线连接，受到每个第一I / O端子的每个第一因子的识别实例与相关联的第二因素的识别实例相关联 的匹配第二个I / O端子。
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10.发明授权
公开(公告)号：US5875011A
公开(公告)日：1999-02-23
申请号：US834861
申请日：1997-04-10
Applicant: Mark Vincent Pierson , Michael Anthony Gaynes , David Brian Stone , Thurston Bryce Youngs
IPC: G02F1/13 , G02F1/1333 , H05K3/34 , H05K3/36 , H05K3/40 , G02F1/133 , G02F1/1345
CPC classification number: G02F1/13452 , G02F1/13336 , H05K3/3442 , H05K3/368 , H05K3/403
Abstract: A liquid crystal display is provided wherein a plurality of liquid crystal display tiles are arranged in a matrix and are electrically interconnected to a tile carrier by depositing an electrically conductive metal on a sidewall edge of the liquid crystal display such as by plating, evaporation, or sputtering. Also provided is the method for forming the liquid crystal display.
Abstract translation: 提供了一种液晶显示器，其中多个液晶显示瓦片以矩阵形式布置并且通过在液晶显示器的侧壁边缘上沉积导电金属而电瓷互连到瓦片载体，例如通过电镀，蒸发或 溅射。 还提供了形成液晶显示器的方法。
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