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公开(公告)号：US08943274B2
公开(公告)日：2015-01-27
申请号：US13477768
申请日：2012-05-22
Applicant: David Louis Spengler , Aaron Danis , William Anthony Pagano
Inventor： David Louis Spengler , Aaron Danis , William Anthony Pagano
CPC classification number: G06F12/0223 , G06F1/30 , G06F12/0864 , G06F12/0871
Abstract: An apparatus and associated method is provided employing data capacity determination logic. The logic dynamically changes a data storage capacity of an electronic data storage memory. The change in capacity is made in relation to a transient energy during a power state change sequence performed by the electronic data storage memory.
Abstract translation: 使用数据容量确定逻辑提供了一种装置和相关方法。 逻辑动态地改变电子数据存储存储器的数据存储容量。 在由电子数据存储存储器执行的功率状态改变序列期间，容量的变化是相对于瞬态能量进行的。
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公开(公告)号：US07727004B2
公开(公告)日：2010-06-01
申请号：US11480087
申请日：2006-06-30
Applicant: David Louis Spengler , Bill A. Pagano
Inventor： David Louis Spengler , Bill A. Pagano
IPC: G01R27/02
CPC classification number: H05K1/0268 , H05K3/306 , H05K3/42 , H05K2201/09627 , H05K2201/1059 , H05K2203/175
Abstract: An apparatus and associated method for analyzing a communications link between two components on a common PCB. The communications link has a pair of through-board conductors connected by a first conductive etching on one side of the PCB. The communications link further has second etchings on an opposite side of the PCB respectively connecting each of the through-board conductors to one of the components. The first conductive etching can operably be open-circuited and connectors of an analyzer can be fitted to the through-board conductors to test the communications link between the components.
Abstract translation: 一种用于分析公共PCB上的两个组件之间的通信链路的装置和相关联的方法。 通信链路具有通过PCB的一侧上的第一导电蚀刻而连接的一对贯通板导体。 通信链路还在PCB的相对侧上具有第二蚀刻，其分别将每个贯通板导体连接到其中一个部件。 第一导电蚀刻可以可操作地开路，并且分析仪的连接器可以安装到贯穿板导体，以测试部件之间的通信链路。
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公开(公告)号：US07544070B2
公开(公告)日：2009-06-09
申请号：US10884330
申请日：2004-07-02
Applicant: David Louis Spengler
Inventor： David Louis Spengler
IPC: H01R13/648
CPC classification number: G06F1/189 , G06F1/187 , H01R13/6471 , H05K1/0216 , H05K2201/09327
Abstract: An electronics cabinet is provided comprising an electrical connector in electrical communication with a printed circuit board (PCB) comprising a PCB power plane, the connector comprising a plurality of power contacts defining a connector power plane adapted for receiving a substantially even power load distribution from the PCB power plane among the power contacts.
Abstract translation: 提供一种电子柜，其包括与包括PCB电源平面的印刷电路板（PCB）电连通的电连接器，所述连接器包括多个电源触点，所述电源触点限定连接器电源平面，所述连接器电源平面适于从 PCB电源平面之间的电源触点。
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Patent Agency Ranking
公开(公告)号：US20080003884A1
公开(公告)日：2008-01-03
申请号：US11480087
申请日：2006-06-30
Applicant: David Louis Spengler , Bill Pagano
Inventor： David Louis Spengler , Bill Pagano
IPC: H01R13/66
CPC classification number: H05K1/0268 , H05K3/306 , H05K3/42 , H05K2201/09627 , H05K2201/1059 , H05K2203/175
Abstract: An apparatus and associated method for analyzing a communications link between two components on a common PCB. The communications link has a pair of through-board conductors connected by a first conductive etching on one side of the PCB. The communications link further has second etchings on an opposite side of the PCB respectively connecting each of the through-board conductors to one of the components.
Abstract translation: 一种用于分析公共PCB上的两个组件之间的通信链路的装置和相关联的方法。 通信链路具有通过PCB的一侧上的第一导电蚀刻而连接的一对贯通板导体。 通信链路还在PCB的相对侧上具有第二蚀刻，其分别将每个贯通板导体连接到其中一个部件。
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公开(公告)号：US20130318299A1
公开(公告)日：2013-11-28
申请号：US13477768
申请日：2012-05-22
Applicant: David Louis Spengler , Aaron Danis , William Anthony Pagano
Inventor： David Louis Spengler , Aaron Danis , William Anthony Pagano
CPC classification number: G06F12/0223 , G06F1/30 , G06F12/0864 , G06F12/0871
Abstract: An apparatus and associated method is provided employing data capacity determination logic. The logic dynamically changes a data storage capacity of an electronic data storage memory. The change in capacity is made in relation to a transient energy during a power state change sequence performed by the electronic data storage memory.
Abstract translation: 使用数据容量确定逻辑提供了一种装置和相关方法。 逻辑动态地改变电子数据存储存储器的数据存储容量。 在由电子数据存储存储器执行的电力状态改变序列期间，容量的变化是相对于瞬态能量进行的。
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公开(公告)号：US07661005B2
公开(公告)日：2010-02-09
申请号：US11479364
申请日：2006-06-30
Applicant: David Louis Spengler , Thomas M. Lawlor , David P. DeCenzo , Bill A. Pagano
Inventor： David Louis Spengler , Thomas M. Lawlor , David P. DeCenzo , Bill A. Pagano
IPC: G06F1/26
CPC classification number: G11B33/126
Abstract: Method and apparatus for controllably applying input power to storage devices in a multi-device array. The array preferably includes a circuit which changes input power state of the storage devices in a time-staggered sequence. Preferably, the change of input power state transitions the array from an operationally deactivated state to an operationally activated state, or vice versa. The storage devices preferably store data in accordance with a selected RAID configuration. A power supply preferably supplies respective first and second direct current (dc) voltages to each of the storage devices, and the circuit respectively connects the dc voltages to the storage devices in a selected sequential order. The circuit further preferably changes an input power state of a single storage device of the array in accordance with a selected time-varying profile. The profile is preferably applied to a gate of a switching device to control a source-drain conduction path.
Abstract translation: 用于可控地向多器件阵列中的存储器件施加输入功率的方法和装置。 阵列优选地包括以时间顺序序列改变存储装置的输入功率状态的电路。 优选地，输入功率状态的改变将阵列从操作失效状态转换到操作激活状态，反之亦然。 存储设备优选地根据所选择的RAID配置来存储数据。 电源优选地将各个第一和第二直流（dc）电压提供给每个存储装置，并且电路以选定的顺序分别将直流电压连接到存储装置。 电路还优选地根据所选择的时变曲线来改变阵列的单个存储装置的输入功率状态。 轮廓优选地施加到开关装置的栅极以控制源极 - 漏极传导路径。
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公开(公告)号：US20080005595A1
公开(公告)日：2008-01-03
申请号：US11479364
申请日：2006-06-30
Applicant: David Louis Spengler , Thomas M. Lawlor , David P. DeCenzo , Bill A. Pagano
Inventor： David Louis Spengler , Thomas M. Lawlor , David P. DeCenzo , Bill A. Pagano
IPC: G06F1/00
CPC classification number: G11B33/126
Abstract: Method and apparatus for controllably applying input power to storage devices in a multi-device array. The array preferably includes a circuit which changes input power state of the storage devices in a time-staggered sequence. Preferably, the change of input power state transitions the array from an operationally deactivated state to an operationally activated state, or vice versa. The storage devices preferably store data in accordance with a selected RAID configuration. A power supply preferably supplies respective first and second direct current (dc) voltages to each of the storage devices, and the circuit respectively connects the dc voltages to the storage devices in a selected sequential order. The circuit further preferably changes an input power state of a single storage device of the array in accordance with a selected time-varying profile. The profile is preferably applied to a gate of a switching device to control a source-drain conduction path.
Abstract translation: 用于可控地向多器件阵列中的存储器件施加输入功率的方法和装置。 阵列优选地包括以时间顺序序列改变存储装置的输入功率状态的电路。 优选地，输入功率状态的改变将阵列从操作失效状态转换到操作激活状态，反之亦然。 存储设备优选地根据所选择的RAID配置来存储数据。 电源优选地将各个第一和第二直流（dc）电压提供给每个存储装置，并且电路以选定的顺序分别将直流电压连接到存储装置。 电路还优选地根据所选择的时变曲线来改变阵列的单个存储装置的输入功率状态。 轮廓优选地施加到开关装置的栅极以控制源极 - 漏极传导路径。
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公开(公告)号：US07177222B2
公开(公告)日：2007-02-13
申请号：US11072818
申请日：2005-03-04
Applicant: David Louis Spengler
Inventor： David Louis Spengler
CPC classification number: G11C11/4074 , G06F1/3203 , G06F1/3275 , G11C11/406 , G11C2211/4067 , Y02D10/14
Abstract: An apparatus and associated method for reducing power consumption in an electronic circuit comprising a refresh load device being employed alternatively between an operational mode and a state refresh mode. A supply voltage level to the refresh load device is adjusted in relation to which of the operational and state refresh modes is employed and in relation to which of a primary alternating current derived power source or a backup battery power source is employed.
Abstract translation: 一种用于降低电子电路中的功耗的装置和相关方法，包括在操作模式和状态刷新模式之间交替使用的刷新负载装置。 调整到刷新负载装置的电源电压相对于采用哪种操作和状态刷新模式，并且相对于采用哪个主要交流电源或备用电池电源。
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