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    REDUCING LOGIC LOCKING KEY LEAKAGE THROUGH THE SCAN CHAIN
    1.
    发明申请
    REDUCING LOGIC LOCKING KEY LEAKAGE THROUGH THE SCAN CHAIN 有权

    公开(公告)号：US20230090772A1

    公开(公告)日：2023-03-23

    申请号：US17480771

    申请日：2021-09-21

    Applicant: Drexel University

    Inventor： Kyle Joseph Juretus ,  Ioannis Savidis

    IPC: G06F21/55 ,  H03K19/20

    Abstract: A proposed technique allows for the security of the logic cone through logic locking and secures the outputs of the circuit from the scan chain without modifications to the structure of the scan chain. Since the oracle responses in test mode do not correspond to the functional key, satisfiability (SAT) attacks are not able to leverage the responses from the scan chain. In addition, a charge accumulation circuit is developed to prevent and detect any attempt to enter the partitioned test mode while the correct circuit responses are still stored within the registers.

    Reducing logic locking key leakage through the scan chain
    2.
    发明授权
    Reducing logic locking key leakage through the scan chain 有权

    公开(公告)号：US11971987B2

    公开(公告)日：2024-04-30

    申请号：US17480771

    申请日：2021-09-21

    Applicant: Drexel University

    Inventor： Kyle Joseph Juretus ,  Ioannis Savidis

    IPC: G06F21/55 ,  G06F21/76

    CPC classification number: G06F21/556 ,  G06F21/76 ,  G06F2221/034

    Abstract: A proposed technique allows for the security of the logic cone through logic locking and secures the outputs of the circuit from the scan chain without modifications to the structure of the scan chain. Since the oracle responses in test mode do not correspond to the functional key, satisfiability (SAT) attacks are not able to leverage the responses from the scan chain. In addition, a charge accumulation circuit is developed to prevent and detect any attempt to enter the partitioned test mode while the correct circuit responses are still stored within the registers.

    Securing analog mixed-signal integrated circuits through shared dependencies
    5.
    发明授权
    Securing analog mixed-signal integrated circuits through shared dependencies 有权

    公开(公告)号：US11270031B2

    公开(公告)日：2022-03-08

    申请号：US16862111

    申请日：2020-04-29

    Applicant: Drexel University

    Inventor： Ioannis Savidis ,  Vaibhav Venugopal Rao ,  Kyle Joseph Juretus

    IPC: G06F21/75 ,  H03K21/02 ,  H03K5/1532 ,  H03M1/36

    Abstract: The transition to a horizontal integrated circuit (IC) design flow has raised concerns regarding the security and protection of IC intellectual property (IP). Obfuscation of an IC has been explored as a potential methodology to protect IP in both the digital and analog domains in isolation. However, novel methods are required for analog mixed-signal circuits that both enhance the current disjoint implementations of analog and digital security measures and prevent an independent adversarial attack of each domain. A methodology generates functional and behavioral dependencies between the analog and digital domains that results in an increase in the adversarial key search space. The dependencies between the analog and digital keys result in a 3× increase in the number of iterations required to complete the SAT attack.

    Enhanced circuity security through hidden state transitions
    7.
    发明申请
    Enhanced circuity security through hidden state transitions 有权

    公开(公告)号：US20210019449A1

    公开(公告)日：2021-01-21

    申请号：US16980471

    申请日：2019-03-13

    Applicant: Drexel University

    Inventor： Kyle Joseph Juretus ,  Ioannis Savidis

    IPC: G06F21/75 ,  G06F21/76 ,  G06F21/79 ,  G06F9/448

    Abstract: A state machine system on a chip presents hidden state transitions to create IC knowledge not available in a logical netlist and temporal key dependencies to increase the difficulty of executing the SAT attack. The change in the state space of a circuit over time may be used to increase circuit security. Hidden transitions that are frequency dependent, state dependent keys, and temporally dependent transition keys may be used as ways to increase security against SAT based attacks.

    SECURING ANALOG MIXED-SIGNAL INTEGRATED CIRCUITS THROUGH SHARED DEPENDENCIES
    8.
    发明申请
    SECURING ANALOG MIXED-SIGNAL INTEGRATED CIRCUITS THROUGH SHARED DEPENDENCIES 审中-公开

    公开(公告)号：US20200342142A1

    公开(公告)日：2020-10-29

    申请号：US16862111

    申请日：2020-04-29

    Applicant: Drexel University

    Inventor： Ioannis Savidis ,  Vaibhav Venugopal Rao ,  Kyle Joseph Juretus

    IPC: G06F21/75 ,  H03M1/36 ,  H03K5/1532 ,  H03K21/02

    Abstract: The transition to a horizontal integrated circuit (IC) design flow has raised concerns regarding the security and protection of IC intellectual property (IP). Obfuscation of an IC has been explored as a potential methodology to protect IP in both the digital and analog domains in isolation. However, novel methods are required for analog mixed-signal circuits that both enhance the current disjoint implementations of analog and digital security measures and prevent an independent adversarial attack of each domain. A methodology generates functional and behavioral dependencies between the analog and digital domains that results in an increase in the adversarial key search space. The dependencies between the analog and digital keys result in a 3× increase in the number of iterations required to complete the SAT attack.

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