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公开(公告)号：US09865381B2
公开(公告)日：2018-01-09
申请号：US15113397
申请日：2015-01-02
Applicant: EPCOS AG
Inventor： Yasuharu Miyauchi , Pavol Dudesek , Christian Faistauer , Gerhard Fuchs , Stefan Obermair , Klaus-Dieter Aichholzer , Christian Block , Sebastian Brunner
CPC classification number: H01C7/12 , C03C3/089 , H01C7/1006 , H01C7/112 , H01C7/18 , H01C17/285 , H01L25/167 , H01L2924/0002 , H01L2924/00
Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.
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2.发明申请Overvoltage Protection Element and Method for Producing an Overvoltage Protection Element 审中-公开过电压保护元件及过压保护元件的制造方法公开(公告)号：US20160329698A1
公开(公告)日：2016-11-10
申请号：US15110701
申请日：2015-01-15
Applicant: EPCOS AG
Inventor： Manfred Schweinzger , Stefan Obermair , Pavol Dudesek
IPC: H02H3/20
Abstract: An overvoltage protection element and a method for producing an overvoltage protection element is disclosed. In an embodiment, the overvoltage protection element includes a first electrode, a second electrode and a discharge region arranged between the first electrode and the second electrode, wherein a porous discharge dielectric is arranged in the discharge region, and wherein the overvoltage protection element is configured to discharge a gas in pores of the discharge dielectric and produce an electrically conductive connection between the first electrode and the second electrode.
Abstract translation: 公开了一种过电压保护元件及其制造方法。 在一个实施例中，过电压保护元件包括第一电极，第二电极和布置在第一电极和第二电极之间的放电区域，其中多孔放电电介质布置在放电区域中，并且其中配置过电压保护元件 以在放电电介质的孔中排出气体，并在第一电极和第二电极之间产生导电连接。
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公开(公告)号：US09691550B2
公开(公告)日：2017-06-27
申请号：US14441467
申请日：2013-10-07
Applicant: EPCOS AG
Inventor： Michael Schossmann , Günter Engel , Stefan Obermair , Bernhard Döllgast , Markus Koini , Jürgen Konrad
CPC classification number: H01G4/30 , B32B7/045 , B32B15/04 , B32B37/0076 , B32B37/18 , B32B2307/202 , B32B2307/204 , B32B2311/00 , B32B2311/14 , B32B2311/18 , B32B2457/16 , H01G4/005 , H01G4/1218 , H01G4/1245 , H01G4/385
Abstract: A multi-layer capacitor has dielectric layers and electrode layers arranged therebetween. The multi-layer capacitor has a number of segments that are connected to one another. At least one relief region is provided between the segments. The invention furthermore provides a method for producing such a multi-layer capacitor.
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4.发明申请公开(公告)号：US20150194264A1
公开(公告)日：2015-07-09
申请号：US14415548
申请日：2013-06-19
Applicant: EPCOS AG
Inventor： Günter Engel , Michael Schossmann , Markus Koini , Jürgen Konrad , Stefan Obermair
CPC classification number: H01G4/228 , H01G2/02 , H01G4/005 , H01G4/1209 , H01G4/1218 , H01G4/2325 , H01G4/30
Abstract: An electrical component is disclosed. In an embodiment the component includes a component body and at least one connection element having a plastic body, wherein the at least one connection element is connected to the component body via a metal layer.
Abstract translation: 公开了电气部件。 在一个实施例中，所述部件包括部件主体和至少一个具有塑料体的连接元件，其中所述至少一个连接元件经由金属层连接到所述部件主体。
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Patent Agency Ranking
5.发明授权公开(公告)号：US10389105B2
公开(公告)日：2019-08-20
申请号：US15110701
申请日：2015-01-15
Applicant: EPCOS AG
Inventor： Manfred Schweinzger , Stefan Obermair , Pavol Dudesek
Abstract: An overvoltage protection element and a method for producing an overvoltage protection element is disclosed. In an embodiment, the overvoltage protection element includes a first electrode, a second electrode and a discharge region arranged between the first electrode and the second electrode, wherein a porous discharge dielectric is arranged in the discharge region, and wherein the overvoltage protection element is configured to discharge a gas in pores of the discharge dielectric and produce an electrically conductive connection between the first electrode and the second electrode.
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公开(公告)号：US20150294792A1
公开(公告)日：2015-10-15
申请号：US14441467
申请日：2013-10-07
Applicant: EPCOS AG
Inventor： Michael Schossmann , Günter Engel , Stefan Obermair , Bernhard Döllgast , Markus Koini , Jürgen Konrad
CPC classification number: H01G4/30 , B32B7/045 , B32B15/04 , B32B37/0076 , B32B37/18 , B32B2307/202 , B32B2307/204 , B32B2311/00 , B32B2311/14 , B32B2311/18 , B32B2457/16 , H01G4/005 , H01G4/1218 , H01G4/1245 , H01G4/385
Abstract: A multi-layer capacitor has dielectric layers and electrode layers arranged therebetween. The multi-layer capacitor has a number of segments that are connected to one another. At least one relief region is provided between the segments. The invention furthermore provides a method for producing such a multi-layer capacitor.
Abstract translation: 多层电容器具有介电层和布置在其间的电极层。 多层电容器具有彼此连接的多个段。 在片段之间提供至少一个释放区域。 本发明还提供了一种制造这种多层电容器的方法。
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公开(公告)号：US09865394B2
公开(公告)日：2018-01-09
申请号：US14415548
申请日：2013-06-19
Applicant: EPCOS AG
Inventor： Günter Engel , Michael Schossmann , Markus Koini , Jürgen Konrad , Stefan Obermair
CPC classification number: H01G4/228 , H01G2/02 , H01G4/005 , H01G4/1209 , H01G4/1218 , H01G4/2325 , H01G4/30
Abstract: An electrical component is disclosed. In an embodiment the component includes a component body and at least one connection element having a plastic body, wherein the at least one connection element is connected to the component body via a metal layer.
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公开(公告)号：US20170011827A1
公开(公告)日：2017-01-12
申请号：US15113397
申请日：2015-01-02
Applicant: EPCOS AG
Inventor： Yasuharu Miyauchi , Pavol Dudesek , Christian Faistauer , Gerhard Fuchs , Stefan Obermair , Klaus-Dieter Aichholzer , Christian Block , Sebastian Brunner
CPC classification number: H01C7/12 , C03C3/089 , H01C7/1006 , H01C7/112 , H01C7/18 , H01C17/285 , H01L25/167 , H01L2924/0002 , H01L2924/00
Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.
Abstract translation: 公开了一种芯片和芯片的制造方法。 在一个实施例中，芯片包括由氧化锌组成的可变电阻层，在压敏电阻层中实现变阻器功能的多层电极结构以及可变阻抗层的第一主表面上的至少两个可焊接或可接合的外部触点。 芯片还包括设置在第一主表面上的玻璃层，仅留下未覆盖的外部触点，其中玻璃层主要包括Si和/或Ge，B和K的氧化物，其总共具有至少70％ 的玻璃层的成分，并且其中玻璃层基本上不含Al，Ga，Cr和Ti。
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公开(公告)号：US20150351258A1
公开(公告)日：2015-12-03
申请号：US14654436
申请日：2013-11-26
Applicant: EPCOS AG
Inventor： Thomas Feichtinger , Axel Pecina , Stefan Obermair , Werner Tschnuchnig
CPC classification number: H05K3/4611 , B32B15/04 , B32B37/06 , B32B37/10 , B32B2305/80 , B32B2457/08 , B32B2457/14 , H01L21/4867 , H01L23/15 , H01L23/3677 , H01L33/642 , H01L2924/0002 , H05K1/0204 , H05K1/16 , H05K3/4629 , Y10T156/10 , Y10T428/24851 , H01L2924/00
Abstract: A method for producing a multilayer carrier body is disclosed. A method for producing a multilayer carrier body. The method includes producing films by printing a first area of each film with a first paste and printing a second area of the film with a second paste. The method also includes stacking the films and laminating the films.
Abstract translation: 公开了一种多层载体的制造方法。 一种多层载体的制造方法。 该方法包括通过用第一浆料印刷每个薄膜的第一区域并用第二浆料印刷薄膜的第二区域来制造薄膜。 该方法还包括层叠薄膜并层压薄膜。
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