公开(公告)号：US20230117490A1

公开(公告)日：2023-04-20

申请号：US17966683

申请日：2022-10-14

Applicant: EPISTAR CORPORATION

Inventor： Chang-Tai HSIAO ,  Ying-Yang SU

IPC: H01L21/683 ,  H01L25/075 ,  H01L33/46 ,  H01L33/62

Abstract: A semiconductor element arrangement structure is provided. The semiconductor element arrangement structure includes a carrier substrate, first and second adhesive layers respectively disposed on the carrier substrate and separated from each other, and first and second semiconductor elements disposed on the first and second adhesive layers, respectively. The first semiconductor element has first and second electrodes on the same side of the first semiconductor element, and the second semiconductor element has third and fourth electrodes on the same side of the second semiconductor element. The first adhesive layer is in direct contact with the first and second electrodes, and the second adhesive layer is in direct contact with the third and fourth electrodes. The first adhesive layer has a first width between the first and second electrodes and has a second width not between the first and second electrodes that is less than the first width.

公开(公告)号：US20250081699A1

公开(公告)日：2025-03-06

申请号：US18817184

申请日：2024-08-27

Applicant: EPISTAR CORPORATION

Inventor： Chang-Tai HSIAO ,  Shih-An LIAO

IPC: H01L33/62 ,  H01L33/22 ,  H01L33/36

Abstract: A semiconductor device comprises a first semiconductor stack comprising a first type semiconductor layer and a second type semiconductor layer; a protecting layer located on the semiconductor stack comprising n first openings and m second openings; a first electrode located on the n first openings, comprising a first outer surface and electrically connected to the first type semiconductor layer; a second electrode located on the m second openings, comprising a second outer surface and electrically connected to the second type semiconductor layer; a first conductive bump located on the first electrode and including a first convex top; a second conductive bump located on the second electrode and comprising a second convex top. The first top and the second top substantially have a same horizontal elevation.

公开(公告)号：US20240405181A1

公开(公告)日：2024-12-05

申请号：US18733304

申请日：2024-06-04

Applicant: EPISTAR CORPORATION

Inventor： Min-Hsun HSIEH ,  Shih-An LIAO ,  Wei-Yu CHEN ,  Li-Shen TANG ,  Kun-Wei KAO ,  Jia-Xing CHUNG ,  Wei-Shan HU ,  Ching-Tai CHENG ,  Chang-Tai HSIAO ,  Yih-Hua RENN ,  Chun-Yen WU

IPC: H01L33/62 ,  H01L25/075 ,  H01L33/40

Abstract: An embodiment of the present disclosure provides a semiconductor device arrangement. This arrangement includes a substrate, an adhesive structure, and a first semiconductor device. The substrate includes an upper surface. The adhesive structure is located on the upper surface and includes a first concave region. The first semiconductor device includes a lower surface facing toward the adhesive structure and a conductive bump located under the lower surface and in the first concave region. The conductive bump includes a first portion and a second portion. Wherein the lower surface does not contact the adhesive structure, the first portion contacts the first concave region, and the second portion does not contact the first concave region.

公开(公告)号：US20240405002A1

公开(公告)日：2024-12-05

申请号：US18734838

申请日：2024-06-05

Applicant: EPISTAR CORPORATION

Inventor： Min-Hsun HSIEH ,  Chang-Tai HSIAO

IPC: H01L25/075 ,  H01L23/00

Abstract: An embodiment of the present disclosure provides a semiconductor device arrangement. This semiconductor device arrangement includes a substrate and a plurality of semiconductor devices. The substrate includes an upper surface. The plurality of semiconductor devices is separately and staggered located on the upper surface, and includes a first semiconductor device and a second semiconductor device. Wherein the first semiconductor device includes a first interior angle, the second semiconductor device includes a second interior angle, and there is a minimum distance between the first interior angle and the second interior angle among the plurality of semiconductor devices, wherein the minimum distance is between 3 μm 25 μm.