公开(公告)号：US20170212800A1

公开(公告)日：2017-07-27

申请号：US15006130

申请日：2016-01-26

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Nikhil SHARMA ,  Rajesh GUPTA ,  Vivek SHARMA

IPC: G06F11/10 ,  G06F11/30 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F11/1016 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/065 ,  G06F3/068 ,  G06F11/3027 ,  G06F13/28 ,  G06F13/404 ,  G06F2201/81 ,  G06F2201/87

Abstract: A system that performs a bus transaction includes a transaction controller and a protection code processing circuit. The transaction controller identifies a set of parameters corresponding to the bus transaction based on address and received control information, and modifies at least one parameter or splits the bus transaction into sub-transactions depending on the parameter values to map the bus transaction to a memory address space. The protection code processing circuit generates and inserts a protection code into data to be written to the memory, and removes a protection code from data read from the memory. The system facilitates error checking without requiring modification of the channels (e.g., bus width) used to read and/or write data to memory.