公开(公告)号：US11588487B1

公开(公告)日：2023-02-21

申请号：US17488338

申请日：2021-09-29

Applicant: Faraday Technology Corp.

Inventor： Prateek Kumar Goyal ,  Chienlung Kung

IPC: H03L7/08 ,  H03L7/081 ,  H04L7/00

Abstract: An eye opening monitor device and an operation method thereof are provided. The eye opening monitor device includes a phase interpolator, a first sampling circuit, a second sampling circuit, and a clock centering circuit. The first sampling circuit samples a data signal according to a data clock to generate first sampled data. The second sampling circuit samples the data signal according to a phase interpolation clock to generate second sampled data. The phase interpolator changes a phase of the phase interpolation clock according to a phase interpolation code. The clock centering circuit counts multiple comparison results of the first sampled data and the second sampled data in multiple clock cycles to obtain an error count value for any one of different phase interpolation codes. The clock centering circuit determines the phase interpolation code provided to the phase interpolator based on the error count values corresponding to different phase interpolation codes.

公开(公告)号：US11831287B2

公开(公告)日：2023-11-28

申请号：US17531811

申请日：2021-11-22

Applicant: Faraday Technology Corp.

Inventor： Prateek Kumar Goyal ,  Raghu Nandan Chepuri ,  Vinod Kumar Jain

IPC: H04B10/00 ,  H03G3/30 ,  H04B10/69 ,  H03M1/12 ,  H03F3/45

CPC classification number: H03G3/3084 ,  H03F3/45 ,  H03M1/12 ,  H04B10/6933 ,  H03F2200/375 ,  H03F2203/45212

Abstract: A method for removing offset in a receiver of an integrated circuit (IC) includes: determining digital codes of differential input voltages of an amplifier in a first receiving lane of the receiver; comparing the digital codes to a digital code corresponding to an optimum common mode voltage (VCM) of the receiver; according to the comparison, determining a bias code for adjusting both the differential input voltages to match the optimum VCM; and inputting the bias code to a bias circuit of the receiver. The first receiving lane of the receiver includes a plurality of amplifiers. The method steps are repeated for each amplifier of the plurality of amplifiers, and then repeated for all receiving lanes of the IC.

公开(公告)号：US11949423B2

公开(公告)日：2024-04-02

申请号：US17846018

申请日：2022-06-22

Applicant: Faraday Technology Corp.

Inventor： Mikhail Tamrazyan ,  Vinod Kumar Jain ,  Prateek Kumar Goyal

IPC: H03L7/18 ,  H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H04L7/00

CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H04L7/0016

Abstract: A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.

公开(公告)号：US20230421158A1

公开(公告)日：2023-12-28

申请号：US17846018

申请日：2022-06-22

Applicant: Faraday Technology Corp.

Inventor： Mikhail Tamrazyan ,  Vinod Kumar Jain ,  Prateek Kumar Goyal

IPC: H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H04L7/00

CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H04L7/0016

Abstract: A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.