公开(公告)号：US10049570B2

公开(公告)日：2018-08-14

申请号：US14918776

申请日：2015-10-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric A. Foreman ,  Sudeep Mandal

IPC: G08G1/0965 ,  G01C21/34 ,  G08G1/087 ,  G01C21/36

Abstract: Various embodiments include approaches for analyzing a set of travel pathways for a priority vehicle. In some cases, an approach includes: obtaining data indicating a location of the priority vehicle and a location of a destination for the priority vehicle; ranking each of a set of paths between the location of the priority vehicle and the location of the destination based upon a travel time for the priority vehicle along the set of paths; and sending instructions to vehicles on a highest-ranked path in the set of paths to initiate providing a right-of-way to the priority vehicle, wherein vehicles closer to the destination along the highest-ranked path are instructed to change a corresponding position prior to vehicles farther from the destination along the highest-ranked path.

公开(公告)号：US09552447B2

公开(公告)日：2017-01-24

申请号：US14695091

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger

IPC: G06F9/455 ,  G06F17/50 ,  G06F1/10

CPC classification number: G06F17/5031 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

Abstract: Disclosed are a system and method that control integrated circuit chip temperature using frequency scaling based on predetermined temperature-frequency settings. During integrated circuit chip operation, a controller causes a variable clock signal generator to adjust the frequency of a clock signal that coordinates operations of an integrated circuit chip based on the temperature of the integrated circuit chip and on predetermined temperature-frequency settings. The temperature-frequency settings are predetermined in order to ensure that the frequency of the clock signal, as adjusted, remains sufficiently high to meet a chip performance specification, but sufficiently low to prevent the temperature from rising above a predetermined maximum temperature in order to limit power consumption. Also disclosed is a method of generating such temperature-frequency settings during timing analysis.

Abstract translation: 公开了使用基于预定温度 - 频率设置的频率缩放来控制集成电路芯片温度的系统和方法。 在集成电路芯片操作期间，控制器使可变时钟信号发生器基于集成电路芯片的温度和预定的温度 - 频率设置来调整协调集成电路芯片的操作的时钟信号的频率。 温度 - 频率设置是预先确定的，以确保调整后的时钟信号的频率保持足够高以满足芯片性能规格，但足够低以防止温度升高到高于预定最大温度以限制 能量消耗。 还公开了一种在定时分析期间产生这种温度 - 频率设置的方法。

公开(公告)号：US20160117433A1

公开(公告)日：2016-04-28

申请号：US14525320

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric A. Foreman ,  Chaitanya Kompalli ,  Sudeep Mandal ,  Sebastian T. Ventrone

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/84

Abstract: As disclosed herein, a method, executed by a computer, for integrated circuit timing variability reduction includes loading a netlist that corresponds to a chip design, where the chip design includes one or more circuits and a plurality of post-fill features, traversing a portion of the netlist corresponding to a circuit, determining a post-fill environment for the circuit from a plurality of post-fill features, and modeling a timing variance for the circuit based on the post-fill environment. The method may also include changing one or more post-fill features to achieve a targeted delay. The method may include generating a report of circuit timing and timing variances. One or more circuits can be concurrently traversed. The timing variance can be modeled with the use of a scaling factor for a standard timing variance. A computer system and computer program product corresponding to the method are also disclosed herein.

Abstract translation: 如本文所公开的，由计算机执行的用于集成电路定时可变性降低的方法包括加载对应于芯片设计的网表，其中芯片设计包括一个或多个电路和多个后填充特征，遍历部分 所述网表对应于电路，从多个后填充特征确定所述电路的填充后环境，以及基于所述填充后环境对所述电路的定时方差进行建模。 该方法还可以包括改变一个或多个后填充特征以实现目标延迟。 该方法可以包括生成电路定时和定时方差的报告。 可以同时遍历一个或多个电路。 定时方差可以用标准时间方差的缩放因子来建模。 本文还公开了与该方法对应的计算机系统和计算机程序产品。

公开(公告)号：US20160378903A1

公开(公告)日：2016-12-29

申请号：US14751222

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nathan Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Gregory M. Schaeffer ,  Stephen G. Shuma ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5018 ,  G06F17/5022 ,  G06F17/5031 ,  G06F17/5036 ,  G06F2217/84

Abstract: Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.

Abstract translation: 方法和系统将集成电路设计接收到计算机化设备中，并对集成电路设计进行分析，以识别集成电路设计部分的物理特征的特征。 这样的方法和系统通过以下方式确定是否查看集成电路设计的一部分的定时值对制造过程变量，电压变量和温度变量（PVT变量）的敏感度：评估部分的物理特征的特性之间的关系 的集成电路设计生成指标值; 并且基于指标值是否在表使用过滤器值范围内，或者：计算定时值对PVT变量的灵敏度; 或从查找表中查找先前确定的定时值对PVT变量的敏感度。

公开(公告)号：US20170083661A1

公开(公告)日：2017-03-23

申请号：US14862652

申请日：2015-09-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Susan K. Lichtensteiger ,  Mark W. Kuemerle ,  Jeffrey G. Hemmett

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

Abstract: Design methods and systems disclosed use a process window-aware timing analysis of an integrated circuit (IC) chip design for improved accuracy. Specifically, a process distribution for the design is defined and divided into process windows. Timing parameter adjustment factors are assigned to the process windows. A timing analysis is performed in order to acquire an initial solution for a timing parameter (e.g., delay, slack or slew). For each specific process window, this initial solution is adjusted by the predetermined timing parameter adjustment factor assigned to that specific process window. The adjusted solutions for the different process windows account for process window-to-process window variations in the widths of distribution of a process parameter (e.g., leakage power) and can be used to predict whether IC chips manufactured according the IC chip design will meet established timing requirements (e.g., required arrival times (RATs)) regardless of where they fall within the process distribution.

公开(公告)号：US09519747B1

公开(公告)日：2016-12-13

申请号：US14751222

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nathan Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Gregory M. Schaeffer ,  Stephen G. Shuma ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5018 ,  G06F17/5022 ,  G06F17/5031 ,  G06F17/5036 ,  G06F2217/84

Abstract: Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.

Abstract translation: 方法和系统将集成电路设计接收到计算机化设备中，并对集成电路设计进行分析，以识别集成电路设计部分的物理特征的特征。 这样的方法和系统通过以下方式确定是否查看集成电路设计的一部分的定时值对制造过程变量，电压变量和温度变量（PVT变量）的敏感度：评估部分的物理特征的特性之间的关系 的集成电路设计生成指标值; 并且基于指标值是否在表使用过滤器值范围内，或者：计算定时值对PVT变量的灵敏度; 或从查找表中查找先前确定的定时值对PVT变量的敏感度。

公开(公告)号：US09619609B1

公开(公告)日：2017-04-11

申请号：US14862652

申请日：2015-09-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Susan K. Lichtensteiger ,  Mark W. Kuemerle ,  Jeffrey G. Hemmett

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

Abstract: Design methods and systems disclosed use a process window-aware timing analysis of an integrated circuit (IC) chip design for improved accuracy. Specifically, a process distribution for the design is defined and divided into process windows. Timing parameter adjustment factors are assigned to the process windows. A timing analysis is performed in order to acquire an initial solution for a timing parameter (e.g., delay, slack or slew). For each specific process window, this initial solution is adjusted by the predetermined timing parameter adjustment factor assigned to that specific process window. The adjusted solutions for the different process windows account for process window-to-process window variations in the widths of distribution of a process parameter (e.g., leakage power) and can be used to predict whether IC chips manufactured according the IC chip design will meet established timing requirements (e.g., required arrival times (RATs)) regardless of where they fall within the process distribution.