公开(公告)号：US20200343142A1

公开(公告)日：2020-10-29

申请号：US16396775

申请日：2019-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： JIEHUI SHU ,  RINUS TEK PO LEE ,  WEI HONG ,  HUI ZANG ,  HONG YU

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/285

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages. The present disclosure further provides a method of forming structures in a semiconductor device by forming a first and second cavities having sidewalls and bottom surfaces in a dielectric structure, where the first cavity has a narrower opening than the second cavity, forming a first material layer in the first and second cavities, forming a protective layer over the first material layer, where the protective layer fills the first cavity and conformally covers the sidewall and the bottom surfaces of the second cavity, performing a first isotropic etch on the protective layer to selectively remove a portion of the protective layer and form a retained portion of the protective layer, performing a second isotropic etch on the first material layer to selectively remove a portion of the first material layer and form a retained portion of the first material layer, removing the retained portion of the protective layer, and forming a second material layer in the first and second cavities, the second material layer being formed on the retained portion of the first material layer.

公开(公告)号：US20210074842A1

公开(公告)日：2021-03-11

申请号：US16568242

申请日：2019-09-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： JIEHUI SHU

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device comprising a substrate with a first fin and a second fin disposed on the substrate. A gate electrode is over the first fin and the second fin. A gate-cut pedestal is positioned between the first fin and the second fin, the gate-cut pedestal having side surfaces and a top surface. A portion of the side surfaces of the gate-cut pedestal is covered by the gate electrode. The gate-cut pedestal has a height that is substantially similar to a height of the first fin or the second fin.

公开(公告)号：US20200211903A1

公开(公告)日：2020-07-02

申请号：US16237757

申请日：2019-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： JIEHUI SHU ,  JESSICA MARY DECHENE ,  HUI ZANG ,  NAVED AHMED SIDDIQUI

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/308

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to methods of forming a two-part trench in a semiconductor device that includes one or more field-effect transistors (FETs). The present method includes forming a semiconductor layer above a substrate, forming a mask layer above the semiconductor layer, forming a mask opening with sidewalls in the mask layer and exposing the semiconductor layer, depositing a profile control layer on the sidewalls of the mask opening, and forming a trench in the semiconductor layer by simultaneously etching the profile control layer and the exposed semiconductor layer, where the etching of the profile control layer forms the trench with top and bottom sections having different widths.

公开(公告)号：US20210050425A1

公开(公告)日：2021-02-18

申请号：US16540042

申请日：2019-08-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： SHESH MANI PANDEY ,  JIEHUI SHU

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device comprises a gate stack structure having upper and lower sidewall portions and a bottom portion. The lower sidewall portions and the bottom portion having a high-k dielectric layer and a metal electrode layer that is positioned over the high-k dielectric layer. The upper sidewall portions having low-k dielectric layers over the lower sidewall portions. The low-k dielectric layers having side surfaces that are substantially coplanar with outer side surfaces of the high-k dielectric layer and are substantially coplanar with inner side surfaces of the metal electrode layer. A metal fill layer is over the metal electrode layer and the high-k dielectric layer in the lower sidewall portions and the bottom portion and between the low-k dielectric layers.

公开(公告)号：US20200303247A1

公开(公告)日：2020-09-24

申请号：US16355853

申请日：2019-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： JIEHUI SHU ,  HUI ZANG ,  SCOTT HOWARD BEASOR ,  DALI SHAO

IPC: H01L21/768 ,  H01L29/417

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to methods of forming a protective liner in transistor devices for protecting one or more gate spacers having a low-K dielectric material. The present disclosure further provides a semiconductor structure including a gate structure having a gate spacer, a trench having upper and lower sidewall portions adjacent to the gate spacer, the trench having a conductive structure over a device element and an adjoining insulative structure over an electrical isolation region, a dielectric liner disposed on the lower sidewall portion of the trench, and a protective liner disposed on the upper sidewall portion of the trench and within the insulative structure.

公开(公告)号：US20200373410A1

公开(公告)日：2020-11-26

申请号：US16423035

申请日：2019-05-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： TUNG-HSING LEE ,  SIPENG GU ,  JIEHUI SHU ,  HAITING WANG ,  ALI RAZAVIEH ,  WENJUN LI ,  KAVYA SREE DUGGIMPUDI ,  TAMILMANI ETHIRAJAN ,  BRADLEY MORGENFELD ,  DAVID NOEL POWER

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/45 ,  H01L21/311 ,  H01L21/285 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor device is provided, which includes providing a plurality of fins over a substrate and forming a plurality of first gate structures having a first gate pitch and a plurality of second gate structures having a second gate pitch traversing across a first and a second set of fins, respectively. The second gate pitch is wider than the first gate pitch. Epitaxial regions are formed between adjacent second gate structures in the second set of fins. A dielectric layer is deposited over the second gate structures and the epitaxial regions. Contact openings are formed in the dielectric layer. At least one of the contact openings is formed over the second gate structure where the second gate structure traverses across the second set of fins. The contact openings are filled with a conductive material to form contact structures electrically coupled to the second gate structures.