公开(公告)号：US20210050425A1

公开(公告)日：2021-02-18

申请号：US16540042

申请日：2019-08-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： SHESH MANI PANDEY ,  JIEHUI SHU

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device comprises a gate stack structure having upper and lower sidewall portions and a bottom portion. The lower sidewall portions and the bottom portion having a high-k dielectric layer and a metal electrode layer that is positioned over the high-k dielectric layer. The upper sidewall portions having low-k dielectric layers over the lower sidewall portions. The low-k dielectric layers having side surfaces that are substantially coplanar with outer side surfaces of the high-k dielectric layer and are substantially coplanar with inner side surfaces of the metal electrode layer. A metal fill layer is over the metal electrode layer and the high-k dielectric layer in the lower sidewall portions and the bottom portion and between the low-k dielectric layers.