公开(公告)号：US09971713B2

公开(公告)日：2018-05-15

申请号：US14701371

申请日：2015-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sameh Asaad ,  Ralph E. Bellofatto ,  Michael A. Blocksome ,  Matthias A. Blumrich ,  Peter Boyle ,  Jose R. Brunheroto ,  Dong Chen ,  Chen-Yong Cher ,  George L. Chiu ,  Norman Christ ,  Paul W. Coteus ,  Kristan D. Davis ,  Gabor J. Dozsa ,  Alexandre E. Eichenberger ,  Noel A. Eisley ,  Matthew R. Ellavsky ,  Kahn C. Evans ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Alan Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Michael K. Gschwind ,  John A. Gunnels ,  Shawn A. Hall ,  Rudolf A. Haring ,  Philip Heidelberger ,  Todd A. Inglett ,  Brant L. Knudson ,  Gerard V. Kopcsay ,  Sameer Kumar ,  Amith R. Mamidala ,  James A. Marcella ,  Mark G. Megerian ,  Douglas R. Miller ,  Samuel J. Miller ,  Adam J. Muff ,  Michael B. Mundy ,  John K. O'Brien ,  Kathryn M. O'Brien ,  Martin Ohmacht ,  Jeffrey J. Parker ,  Ruth J. Poole ,  Joseph D. Ratterman ,  Valentina Salapura ,  David L. Satterfield ,  Robert M. Senger ,  Burkhard Steinmacher-Burow ,  William M. Stockdell ,  Craig B. Stunkel ,  Krishnan Sugavanam ,  Yutaka Sugawara ,  Todd E. Takken ,  Barry M. Trager ,  James L. Van Oosten ,  Charles D. Wait ,  Robert E. Walkup ,  Alfred T. Watson ,  Robert W. Wisniewski ,  Peng Wu

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/28 ,  G06F15/173 ,  G06F15/76 ,  G06F9/06 ,  G06F12/0862 ,  G06F12/0864 ,  G06F15/80 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/1027

CPC classification number: G06F13/287 ,  G06F9/06 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/3885 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/1027 ,  G06F15/17381 ,  G06F15/17387 ,  G06F15/76 ,  G06F15/8069 ,  G06F2212/1016 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6024 ,  G06F2212/6032 ,  Y02D10/13 ,  Y02D10/14

Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

公开(公告)号：US09733831B2

公开(公告)日：2017-08-15

申请号：US14320841

申请日：2014-07-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Martin Ohmacht

IPC: G06F3/00 ,  G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F13/16 ,  G11C7/22

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0671 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/522 ,  G06F13/1689 ,  G06F2003/0697 ,  G11C7/22

Abstract: In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

公开(公告)号：US09405596B2

公开(公告)日：2016-08-02

申请号：US14504832

申请日：2014-10-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hans Boettiger ,  Yaoqing Gao ,  Martin Ohmacht ,  Kai-Ting Amy Wang

IPC: G06F9/45 ,  G06F9/52

CPC classification number: G06F9/528 ,  G06F8/4436 ,  G06F8/452

Abstract: Code versioning for enabling transactional memory region promotion may include receiving a portion of candidate source code; outlining the portion of candidate source code received for parallel execution; wrapping a critical region with entry and exit routines to enter into a speculation sub-process, wherein the entry and exit routines also gather conflict statistics at run time; and generating an outlined code portion comprising multiple loop versions using a processor.

Abstract translation: 用于启用事务性存储器区域升级的代码版本化可以包括接收候选源代码的一部分; 概述接收并行执行的候选源代码的部分; 用入口和出口例程包装关键区域以进入推测子过程，其中进入和退出例程还在运行时收集冲突统计; 以及使用处理器生成包括多个循环版本的概述代码部分。