中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.036 seconds)

    Optimization of instruction groups across group boundaries
    1.
    发明授权
    Optimization of instruction groups across group boundaries 有权
    跨组界限的指令组优化

    公开(公告)号：US09372695B2

    公开(公告)日：2016-06-21

    申请号：US13931680

    申请日：2013-06-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Michael K. Gschwind

    IPC: G06F9/30 ,  G06F9/45 ,  G06F9/38 ,  G06F9/455

    CPC classification number: G06F9/30145 ,  G06F8/41 ,  G06F8/433 ,  G06F8/443 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/455

    Abstract: Instructions grouped into instruction groups are optimized across group boundaries. Instruction sequences spanning multiple groups are optimized by retaining information relating to an instruction at the end of one instruction group to be co-optimized with an instruction at the beginning of a subsequent instruction group. This retained information is then used in optimization of one or more instructions of the subsequent group. Optimization may be performed across n group boundaries, where n is equal to two or greater. Additionally, optimization of instructions within a group may be performed, in addition to the optimizations across group boundaries.

    Abstract translation: 分组到指令组的指令在组边界之间进行了优化。 跨越多个组的指令序列通过保留与一个指令组的结尾处的指令相关的信息来优化，以与后续指令组的开始处的指令进行共同优化。 然后将该保留的信息用于优化后续组的一个或多个指令。 可以在n个组边界上执行优化，其中n等于2或更大。 此外，除了跨组边界的优化之外，还可以执行组内的指令的优化。

    Managing high-conflict cache lines in transactional memory computing environments
    2.
    发明授权
    Managing high-conflict cache lines in transactional memory computing environments 有权
    在事务性内存计算环境中管理高冲突缓存行

    公开(公告)号：US09298626B2

    公开(公告)日：2016-03-29

    申请号：US14037879

    申请日：2013-09-26

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael K. Gschwind ,  Maged M. Michael ,  Valentina Salapura ,  Eric M. Schwarz ,  Chung-Lung K. Shum

    IPC: G06F13/12 ,  G06F12/08 ,  G06F9/30

    CPC classification number: G06F12/0828 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831

    Abstract: Cache lines in a computing environment with transactional memory are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. When a transaction accessing a cache line in full-line coherency mode results in a transactional abort, the cache line may be placed in sub-line coherency mode if the cache line is a high-conflict cache line. The cache line may be associated with a counter in a conflict address detection table that is incremented whenever a transaction conflict is detected for the cache line. The cache line may be a high-conflict cache line when the counter satisfies a high-conflict criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.

    Abstract translation: 具有事务性存储器的计算环境中的高速缓存行可使用一致性模式进行配置。 全线一致性模式下的高速缓存行以全行粒度运行或管理。 子行一致性模式下的高速缓存行作为完整高速缓存行的子高速缓存行部分进行操作或管理。 当以全线一致性模式访问高速缓存行的事务导致事务中止时，如果高速缓存行是高冲突高速缓存行，则高速缓存行可以被置于子行一致性模式。 高速缓存行可以与冲突地址检测表中的计数器相关联，每当检测到高速缓存行的事务冲突时，它将递增。 当计数器满足诸如达到阈值的高冲突标准时，高速缓存行可以是高冲突高速缓存行。 当满足复位标准时，高速缓存行可以返回到全线一致性模式。

    Identifying high-conflict cache lines in transactional memory computing environments
    3.
    发明授权
    Identifying high-conflict cache lines in transactional memory computing environments 有权
    在事务性内存计算环境中识别高冲突缓存行

    公开(公告)号：US09298623B2

    公开(公告)日：2016-03-29

    申请号：US14037901

    申请日：2013-09-26

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael K. Gschwind ,  Maged M. Michael ,  Valentina Salapura ,  Eric M. Schwarz ,  Chung-Lung K. Shum

    IPC: G06F13/12 ,  G06F12/08 ,  G06F9/46

    CPC classification number: G06F12/0815 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0831 ,  G06F2212/1016 ,  G06F2212/502

    Abstract: Cache lines in a computing environment with transactional memory are configurable with a coherency mode and are associated with a high-conflict indicator. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. A cache line is placed in sub-line coherency mode based on examining the high-conflict indicator. A transaction accessing a memory address in a cache line in sub-line coherency mode marks only the sub-cache line portion associated with the memory address as transactionally accessed. The high-conflict indicator may be included in a set of descriptive bits associated with the cache line. A copy of the high-conflict indicator for a cache line in a first cache may be updated with the high-conflict indicator for the cache line in a second cache.

    Abstract translation: 具有事务性存储器的计算环境中的高速缓存行可使用一致性模式进行配置，并与高冲突指示器相关联。 全线一致性模式下的高速缓存行以全行粒度运行或管理。 子行一致性模式下的高速缓存行作为完整高速缓存行的子高速缓存行部分进行操作或管理。 基于检查高冲突指标，缓存行被置于子行一致性模式中。 以子行一致性模式访问高速缓存行中的存储器地址的事务仅将与存储器地址相关联的子高速缓存行部分标记为事务访问。 高冲突指示符可以被包括在与高速缓存行相关联的一组描述性位中。 可以用第二高速缓存中的高速缓存行的高冲突指示符来更新第一高速缓存中的高速缓存行的高冲突指示符的副本。

    Predictor data structure for use in pipelined processing
    4.
    发明授权
    Predictor data structure for use in pipelined processing 有权
    用于流水线处理的预测数据结构

    公开(公告)号：US09513924B2

    公开(公告)日：2016-12-06

    申请号：US13931671

    申请日：2013-06-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Michael K. Gschwind ,  Valentina Salapura

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3861 ,  G06F9/30054 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3806 ,  G06F9/382 ,  G06F9/384

    Abstract: A predictor data structure is used for pipelined processing by a pipelined processor. The predictor data structure includes a predicted address to be used in return from execution of a selected instruction, and a predicted operating state associated with the predicted address. Based on determining a selected return instruction is to be executed, the predicted address to which processing is to be returned is obtained from the predictor data structure. Further, based on determining the selected return instruction is to be executed, a transitional operating state to be entered based on the predicted operating state stored in the predictor data structure is predicted, wherein at least one of the predicted address and the predicted transitional operating state are to be used to validate execution of the selected return instruction.

    Abstract translation: 预测器数据结构用于流水线处理器的流水线处理。 预测器数据结构包括从所选择的指令的执行中返回使用的预测地址以及与预测地址相关联的预测操作状态。 基于确定要执行所选择的返回指令，从预测器数据结构获得要返回处理的预测地址。 此外，基于确定要执行所选择的返回指令，预测将基于存储在预测器数据结构中的预测操作状态输入的过渡操作状态，其中预测地址和预测的过渡操作状态中的至少一个 将用于验证所选返回指令的执行。

    Predictor data structure for use in pipelined processing
    5.
    发明授权
    Predictor data structure for use in pipelined processing 有权
    用于流水线处理的预测数据结构

    公开(公告)号：US09535703B2

    公开(公告)日：2017-01-03

    申请号：US14559087

    申请日：2014-12-03

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Michael K. Gschwind ,  Valentina Salapura

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3861 ,  G06F9/30054 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3806 ,  G06F9/382 ,  G06F9/384

    Abstract: A predictor data structure is used for pipelined processing by a pipelined processor. The predictor data structure includes a predicted address to be used in return from execution of a selected instruction, and a predicted operating state associated with the predicted address. Based on determining a selected return instruction is to be executed, the predicted address to which processing is to be returned is obtained from the predictor data structure. Further, based on determining the selected return instruction is to be executed, a transitional operating state to be entered based on the predicted operating state stored in the predictor data structure is predicted, wherein at least one of the predicted address and the predicted transitional operating state are to be used to validate execution of the selected return instruction.

    Abstract translation: 预测器数据结构用于流水线处理器的流水线处理。 预测器数据结构包括从所选择的指令的执行中返回使用的预测地址以及与预测地址相关联的预测操作状态。 基于确定要执行所选择的返回指令，从预测器数据结构获得要返回处理的预测地址。 此外，基于确定要执行所选择的返回指令，预测将基于存储在预测器数据结构中的预测操作状态输入的过渡操作状态，其中预测地址和预测的过渡操作状态中的至少一个 将用于验证所选返回指令的执行。

    Predictive fetching and decoding for selected return instructions
    6.
    发明授权
    Predictive fetching and decoding for selected return instructions 有权
    针对所选择的返回指令进行预测提取和解码

    公开(公告)号：US09361146B2

    公开(公告)日：2016-06-07

    申请号：US14557759

    申请日：2014-12-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Michael K. Gschwind ,  Valentina Salapura

    IPC: G06F9/38 ,  G06F9/455 ,  G06F9/30

    CPC classification number: G06F9/45558 ,  G06F9/30054 ,  G06F9/30145 ,  G06F9/3806 ,  G06F9/384 ,  G06F9/3861

    Abstract: Predictive fetching and decoding for selected instructions. A determination is made as to whether an instruction to be executed in a pipelined processor is a selected return instruction, the pipelined processor having a plurality of stages including an execute stage. Based on the instruction being the selected return instruction, obtaining from a data structure a predicted return address, the predicted return address being an address of an instruction to which it is predicted that processing is to be returned. Additionally, based on the instruction being the selected return instruction, operating state for the instruction at the predicted return address is predicted. The instruction is fetched at the predicted return address, prior to the selected return instruction reaching the execute stage, and decoding of the fetched instruction is initiated based on the predicted operating state.

    Abstract translation: 针对所选指令进行预测提取和解码。 确定在流水线处理器中执行的指令是否是所选择的返回指令，所述流水线处理器具有包括执行阶段的多个级。 基于作为所选择的返回指令的指令，从数据结构获得预测的返回地址，预测的返回地址是预测该处理被返回的指令的地址。 另外，基于作为所选择的返回指令的指令，预测在预测返回地址处的指令的操作状态。 在所选择的返回指令到达执行阶段之前，在预测的返回地址获取指令，并且基于预测的操作状态来启动取出的指令的解码。

    Predictive fetching and decoding for selected return instructions
    7.
    发明授权
    Predictive fetching and decoding for selected return instructions 有权

    公开(公告)号：US09361144B2

    公开(公告)日：2016-06-07

    申请号：US13931635

    申请日：2013-06-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Michael K. Gschwind ,  Valentina Salapura

    IPC: G06F9/30 ,  G06F9/455 ,  G06F9/38

    CPC classification number: G06F9/45558 ,  G06F9/30054 ,  G06F9/30145 ,  G06F9/3806 ,  G06F9/384 ,  G06F9/3861

    Abstract: Predictive fetching and decoding for selected instructions. A determination is made as to whether an instruction to be executed in a pipelined processor is a selected return instruction, the pipelined processor having a plurality of stages including an execute stage. Based on the instruction being the selected return instruction, obtaining from a data structure a predicted return address, the predicted return address being an address of an instruction to which it is predicted that processing is to be returned. Additionally, based on the instruction being the selected return instruction, operating state for the instruction at the predicted return address is predicted. The instruction is fetched at the predicted return address, prior to the selected return instruction reaching the execute stage, and decoding of the fetched instruction is initiated based on the predicted operating state.

    Managing high-coherence-miss cache lines in multi-processor computing environments
    10.
    发明授权
    Managing high-coherence-miss cache lines in multi-processor computing environments 有权
    在多处理器计算环境中管理高连贯错过的高速缓存行

    公开(公告)号：US09329890B2

    公开(公告)日：2016-05-03

    申请号：US14037925

    申请日：2013-09-26

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael K. Gschwind ,  Maged M. Michael ,  Valentina Salapura ,  Eric M. Schwarz ,  Chung-Lung K. Shum

    IPC: G06F13/12 ,  G06F9/46 ,  G06F12/08 ,  G06F3/038 ,  G06F1/16 ,  G06F13/38

    CPC classification number: G06F9/467 ,  G06F1/1632 ,  G06F3/038 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/385 ,  G06F2212/1016 ,  G06F2212/502

    Abstract: Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. A high-coherence-miss cache line may be placed in sub-line coherency mode. A cache line may be associated with a counter in a coherence miss detection table that is incremented whenever an access of the cache line results in a coherence request. The cache line may be a high-coherence-miss cache line when the counter satisfies a high-coherence-miss criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.

    Abstract translation: 多处理器计算环境中的高速缓存行可通过一致性模式进行配置。 全线一致性模式下的高速缓存行以全行粒度运行或管理。 子行一致性模式下的高速缓存行作为完整高速缓存行的子高速缓存行部分进行操作或管理。 高相干缺失高速缓存线可以被置于子线一致性模式中。 高速缓存行可以与相干未验证表中的计数器相关联，每当高速缓存行的访问导致一致性请求时，其将递增。 当计数器满足诸如达到阈值的高相干错误准则时，高速缓存行可以是高相干错失高速缓存行。 当满足复位标准时，高速缓存行可以返回到全线一致性模式。

Patent Agency Ranking