公开(公告)号：US08716094B1

公开(公告)日：2014-05-06

申请号：US13682769

申请日：2012-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Seo Park ,  Linus Jang ,  Jin Cho

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/311

CPC classification number: H01L29/66742 ,  H01L29/66795

Abstract: Approaches for forming a FinFET device using double patterning memorization techniques are provided. Specifically, a device will initially be formed by defining a set of fins, depositing a poly-silicon layer, and depositing a hardmask. Thereafter, a front end of the line (FEOL) lithography-etch, lithography-etch (LELE) process will be performed to form a set of trenches in the device. The set of trenches will be filled with an oxide layer that is subsequently polished. Thereafter, the device is selectively etched to yield a (e.g., poly-silicon) gate pattern.

Abstract translation: 提供了使用双重图案记忆技术形成FinFET器件的方法。 具体来说，首先将通过限定一组翅片，沉积多晶硅层和沉积硬掩模来形成器件。 此后，将执行线的前端（FEOL）光刻蚀刻，光刻蚀刻（LELE）处理以在器件中形成一组沟槽。 该组沟槽将填充随后抛光的氧化物层。 此后，选择性地蚀刻器件以产生（例如，多晶硅）栅极图案。

公开(公告)号：US20190259668A1

公开(公告)日：2019-08-22

申请号：US15899986

申请日：2018-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Seo Park ,  Haiting Wang ,  Shimpei Yamaguchi ,  Junsic Hong ,  Yong Mo Yang ,  Scott Beasor

IPC: H01L21/8234 ,  H01L27/088

Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.

公开(公告)号：US20190131429A1

公开(公告)日：2019-05-02

申请号：US15797837

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Chang Seo Park ,  Shimpei Yamaguchi ,  Tao Han ,  Yong Mo Yang ,  Jinping Liu ,  Hyuck Soo Yang

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.

公开(公告)号：US10832966B2

公开(公告)日：2020-11-10

申请号：US15899986

申请日：2018-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Seo Park ,  Haiting Wang ,  Shimpei Yamaguchi ,  Junsic Hong ,  Yong Mo Yang ,  Scott Beasor

IPC: H01L27/115 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.

公开(公告)号：US10453936B2

公开(公告)日：2019-10-22

申请号：US15797837

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Chang Seo Park ,  Shimpei Yamaguchi ,  Tao Han ,  Yong Mo Yang ,  Jinping Liu ,  Hyuck Soo Yang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.

公开(公告)号：US20190355832A1

公开(公告)日：2019-11-21

申请号：US16523340

申请日：2019-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Chang Seo Park ,  Shimpei Yamaguchi ,  Tao Han ,  Yong Mo Yang ,  Jinping Liu ,  Hyuck Soo Yang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.