公开(公告)号：US20170358565A1

公开(公告)日：2017-12-14

申请号：US15177417

申请日：2016-06-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ulrich Hensel ,  Michael Zier ,  Navneet Jain ,  Rainer Mann

IPC: H01L27/02 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/06 ,  H01L21/28 ,  H01L21/762 ,  H01L29/10 ,  H01L29/423 ,  H01L27/092 ,  H01L29/788

CPC classification number: H01L27/0207 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/11807 ,  H01L2027/11874

Abstract: The present disclosure provides an integrated circuit product including a plurality of standard cells, each standard cell of the plurality of standard cells being in abutment with at least one other standard cell of the plurality of standard cells, a continuous active region continuously extending across the plurality of standard cells, at least two active regions being separated by an intermediate diffusion break, wherein each standard cell comprises at least one PMOS device and at least one NMOS device, the at least one PMOS device being provided in and above the continuous active region and the at least one NMOS device being provided in and above the at least two active regions.

公开(公告)号：US20150213185A1

公开(公告)日：2015-07-30

申请号：US14166044

申请日：2014-01-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ulrich Hensel ,  Rainer Mann

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068

Abstract: A method includes obtaining a plurality of design rules for an integrated circuit, including a first set of design rules and a second set of design rules. An automated layout construction process performed on the basis of the first set of design rules but not on the basis of the second set of design rules creates a layout of the integrated circuit. The layout of the integrated circuit is checked for design rule violations wherein at least one member of the second set of design rules is not satisfied. The layout of the integrated circuit is modified for bringing the layout into conformity with each of the plurality of design rules if one or more design rule violations are found in the checking of the integrated circuit.

Abstract translation: 一种方法包括获得集成电路的多个设计规则，包括第一组设计规则和第二组设计规则。 基于第一组设计规则而不是基于第二组设计规则执行的自动布局构造过程创建了集成电路的布局。 检查集成电路的布局是否符合第二组设计规则的至少一个成员的设计规则违规。 如果在集成电路的检查中发现了一个或多个设计规则违规，则对该集成电路的布局进行了修改，以使布局符合多个设计规则中的每一个。

公开(公告)号：US09613175B2

公开(公告)日：2017-04-04

申请号：US14166044

申请日：2014-01-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ulrich Hensel ,  Rainer Mann

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068

Abstract: A method includes obtaining a plurality of design rules for an integrated circuit, including a first set of design rules and a second set of design rules. An automated layout construction process performed on the basis of the first set of design rules but not on the basis of the second set of design rules creates a layout of the integrated circuit. The layout of the integrated circuit is checked for design rule violations wherein at least one member of the second set of design rules is not satisfied. The layout of the integrated circuit is modified for bringing the layout into conformity with each of the plurality of design rules if one or more design rule violations are found in the checking of the integrated circuit.