公开(公告)号：US20150377956A1

公开(公告)日：2015-12-31

申请号：US14314693

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： William MCMAHON ,  Andreas KERBER ,  Luigi PANTISANO ,  Suresh UPPAL

IPC: G01R31/28

CPC classification number: G01R31/2875 ,  G01R31/2879

Abstract: A methodology for inline characterization and temperature profiling that enables parallel measurement of device characteristics at multiple temperatures and the resulting device are disclosed. Embodiments may include calibrating a first device under test (DUT) with respect to at least one heating structure in a metal layer of an integrated circuit (IC), applying a heater voltage to the at least one heating structure, and measuring at least one characteristic of the first DUT at a first temperature corresponding to the heater voltage.

Abstract translation: 公开了一种在线表征和温度分析的方法，其可以在多个温度下平行测量器件特性，并且得到所得到的器件。 实施例可以包括相对于集成电路（IC）的金属层中的至少一个加热结构校准被测试的第一器件（DUT），向至少一个加热结构施加加热器电压，以及测量至少一个特性 在与加热器电压对应的第一温度下的第一DUT。

公开(公告)号：US20160025805A1

公开(公告)日：2016-01-28

申请号：US14337290

申请日：2014-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suresh UPPAL ,  Randy W. MANN ,  William McMahon

IPC: G01R31/28 ,  H01L21/66 ,  H01L23/525

CPC classification number: G01R31/2884 ,  G01R31/2644 ,  H01L22/14 ,  H01L22/34 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure.

Abstract translation: 描述了晶片测试结构和提供晶片测试结构的方法。 这些方法包括：在晶片上制造多个测试装置和多个保险丝装置，每个测试装置具有与其相关联的相应的熔丝装置，其在测试装置故障时断开电路; 以及制造选择电路，其操作以选择性地将一个测试装置连接到感测触点焊盘，并且将其它测试装置连接到应力接触焊盘。 选择电路通过与感测接触焊盘的电接触便于感测一个测试装置的一个或多个电信号，同时通过与应力接触焊盘电接触来测试其它测试装置。 在一个实施例中，每个测试装置具有相应的第一和第二开关装置，其可操作以选择性地将测试装置电连接到感测或应力接触垫。 在另一个实施例中，该方法包括使用测试结构的晶片测试。

公开(公告)号：US20160163398A1

公开(公告)日：2016-06-09

申请号：US14680228

申请日：2015-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Akhilesh GAUTAM ,  Suresh UPPAL

IPC: G11C17/12 ,  H01L27/112

CPC classification number: G11C17/12 ,  G01R31/26 ,  H01L22/34 ,  H01L27/11206 ,  H01L29/205

Abstract: A method of forming an OTPROM capable of storing twice the number of bits as a conventional OTPROM without increasing the overall size of the device is provided. Embodiments include forming a OTPROM, the OTPROM array having a plurality of formed devices; receiving a binary code to program the OTPROM array; separating the binary code into a first part and a second part; programming each device with one of four data storage states by: forming a gate oxide layer of each device to a thickness corresponding to the first part of the binary code, and selectively applying a TDDB stress to the gate oxide layer corresponding to the second part of the binary code; detecting a Idsat level discharged by each device with a multi-bit sense amplifier; and reading the state of each device based on the detected Idsat level.

Abstract translation: 提供了一种形成能够存储两倍于常规OTPROM的位数的OTPROM的方法，而不增加设备的总体大小。 实施例包括形成OTPROM，OTPROM阵列具有多个形成的器件; 接收二进制代码来编程OTPROM阵列; 将二进制代码分离成第一部分和第二部分; 通过以下方式对每个器件进行编程：通过以下方式对每个器件进行编程：将每个器件的栅极氧化层形成为与二进制代码的第一部分对应的厚度，并且选择性地将TDDB应力施加到对应于第二部分的栅极氧化物层 二进制代码; 用多位读出放大器检测每个器件放电的Idsat电平; 并且基于检测到的Idsat级别读取每个设备的状态。

公开(公告)号：US20160054383A1

公开(公告)日：2016-02-25

申请号：US14462643

申请日：2014-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anil KUMAR ,  Suresh UPPAL ,  Manjunatha PRABHU ,  William MCMAHON

IPC: G01R31/28 ,  G01R31/26

CPC classification number: G01R31/2884 ,  G01R31/2601 ,  G01R31/2644 ,  H01L22/34

Abstract: There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle.

Abstract translation: 这里提出了包括多个测试装置的半导体结构，所述多个测试装置包括第一测试装置和第二测试装置。 半导体结构还可以包括波形发生电路，波形发生电路被配置为将第一应力信号波形具有第一占空比施加到第一测试装置，第二应力信号波形具有第二占空比到第二测试 设备。 半导体结构可以包括与第一测试装置和第二测试装置中的每一个相关联的选择电路，用于在应力循环和感测周期之间切换。