公开(公告)号：US20230132912A1

公开(公告)日：2023-05-04

申请号：US17515914

申请日：2021-11-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： James P. Mazza ,  Elizabeth Strehlow ,  Motoi Ichihashi ,  Xuelian Zhu ,  Jia Zeng

IPC: H01L29/423 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.

公开(公告)号：US20240222356A1

公开(公告)日：2024-07-04

申请号：US18149279

申请日：2023-01-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： James P. Mazza ,  Jia Zeng ,  Xuelian Zhu ,  Navneet K. Jain ,  Mahbub Rashed ,  Jacob Mazza

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.

公开(公告)号：US12002869B2

公开(公告)日：2024-06-04

申请号：US17901887

申请日：2022-09-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4975 ,  H01L21/28 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/41775 ,  H01L29/66477 ,  H01L29/783

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

公开(公告)号：US20240021621A1

公开(公告)日：2024-01-18

申请号：US17812790

申请日：2022-07-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： James P. Mazza ,  Xuelian Zhu ,  Jia Zeng, JR. ,  Navneet Jain ,  Mahbub Rashed

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: An integrated circuit (IC) structure includes a plurality of cell rows with each cell row including a plurality of (standard) cells. A power rail for at least one pair of adjacent cell rows is asymmetric relative to a cell boundary between adjacent cells of the at least one pair of adjacent cell rows. Embodiments of the disclosure can also include the standard cell including a plurality of transistors at a device layer, and at least a portion of an isolation area at an edge of the device layer defining a cell boundary. The standard cell also includes the power rail including a first portion within the cell boundary and a second portion outside the cell boundary. The first portion and the second portion have different heights such that the power rail is asymmetric across the cell boundary. The asymmetric power rail provides seamless integration of cell libraries having different heights.

公开(公告)号：US20220416054A1

公开(公告)日：2022-12-29

申请号：US17901887

申请日：2022-09-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L27/088 ,  H01L27/092

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

公开(公告)号：US11469309B2

公开(公告)日：2022-10-11

申请号：US16804264

申请日：2020-02-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

公开(公告)号：US12046651B2

公开(公告)日：2024-07-23

申请号：US17515914

申请日：2021-11-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： James P. Mazza ,  Elizabeth Strehlow ,  Motoi Ichihashi ,  Xuelian Zhu ,  Jia Zeng

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L29/42376 ,  H01L23/5286

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.