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    System and method employing power-optimized timing closure
    2.
    发明授权
    System and method employing power-optimized timing closure 有权

    公开(公告)号：US12260163B2

    公开(公告)日：2025-03-25

    申请号：US17679178

    申请日：2022-02-24

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Mahbub Rashed

    IPC: G06F30/39 ,  G06F30/392 ,  G06F30/398 ,  G06F111/04 ,  G06F111/20

    Abstract: Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

    SYSTEM AND METHOD EMPLOYING POWER-OPTIMIZED TIMING CLOSURE
    4.
    发明公开
    SYSTEM AND METHOD EMPLOYING POWER-OPTIMIZED TIMING CLOSURE 审中-公开

    公开(公告)号：US20230267259A1

    公开(公告)日：2023-08-24

    申请号：US17679178

    申请日：2022-02-24

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Mahbub Rashed

    IPC: G06F30/392 ,  G06F30/398

    CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F2111/20

    Abstract: Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

    SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
    5.
    发明公开
    SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION 审中-公开

    公开(公告)号：US20230163134A1

    公开(公告)日：2023-05-25

    申请号：US17533402

    申请日：2021-11-23

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Nigel Chan ,  Mahbub Rashed

    IPC: H01L27/12

    CPC classification number: H01L27/1207

    Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P− silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

    INTEGRATED CIRCUIT STRUCTURE WITH CELLS HAVING ASYMMETRIC POWER RAIL
    6.
    发明公开
    INTEGRATED CIRCUIT STRUCTURE WITH CELLS HAVING ASYMMETRIC POWER RAIL 审中-公开

    公开(公告)号：US20240021621A1

    公开(公告)日：2024-01-18

    申请号：US17812790

    申请日：2022-07-15

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： James P. Mazza ,  Xuelian Zhu ,  Jia Zeng, JR. ,  Navneet Jain ,  Mahbub Rashed

    IPC: H01L27/118 ,  H01L27/02

    CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11875 ,  H01L2027/11881

    Abstract: An integrated circuit (IC) structure includes a plurality of cell rows with each cell row including a plurality of (standard) cells. A power rail for at least one pair of adjacent cell rows is asymmetric relative to a cell boundary between adjacent cells of the at least one pair of adjacent cell rows. Embodiments of the disclosure can also include the standard cell including a plurality of transistors at a device layer, and at least a portion of an isolation area at an edge of the device layer defining a cell boundary. The standard cell also includes the power rail including a first portion within the cell boundary and a second portion outside the cell boundary. The first portion and the second portion have different heights such that the power rail is asymmetric across the cell boundary. The asymmetric power rail provides seamless integration of cell libraries having different heights.

    METHOD FOR PERFORMING DESIGN RULE CHECKS
    7.
    发明申请
    METHOD FOR PERFORMING DESIGN RULE CHECKS 有权

    公开(公告)号：US20240370632A1

    公开(公告)日：2024-11-07

    申请号：US18312514

    申请日：2023-05-04

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Romain FEUILLETTE ,  Nolan Pavek ,  Navneet Jain ,  Adam Zeeb ,  Bowen Zhal

    IPC: G06F30/398

    Abstract: A process for performing a design rule check (DRC) by a computer may comprise receiving a DRC result comprising a plurality of DRC errors, the DRC result corresponding to a DRC deck comprising a plurality of rules and a design layout database comprising a plurality of components; classifying, using a neural network, each of the plurality of DRC errors according to whether that DRC should be ignored; and producing a final report including a plurality of respective indications of whether the plurality of DRC errors should be ignored. Performing the process may further include the receiving mistake feedback regarding the final report; updating, using the mistake feedback, a DRC result dataset comprising a plurality of dataset entries; and re-training the neural network using the updated DRC result dataset.

    SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
    8.
    发明公开
    SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION 审中-公开

    公开(公告)号：US20240282776A1

    公开(公告)日：2024-08-22

    申请号：US18653473

    申请日：2024-05-02

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Nigel Chan ,  Mahbub Rashed

    IPC: H01L27/12

    CPC classification number: H01L27/1207

    Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P-silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

    Semiconductor structure including sectioned well region
    9.
    发明授权
    Semiconductor structure including sectioned well region 有权

    公开(公告)号：US12046603B2

    公开(公告)日：2024-07-23

    申请号：US17533402

    申请日：2021-11-23

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Nigel Chan ,  Mahbub Rashed

    IPC: H01L27/12

    CPC classification number: H01L27/1207

    Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P− silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

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