公开(公告)号：US20240035898A1

公开(公告)日：2024-02-01

申请号：US17874709

申请日：2022-07-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhixing ZHAO ,  Yiching CHEN ,  Oscar D. RESTREPO

IPC: G01K7/18 ,  H01L29/66

CPC classification number: G01K7/186 ,  H01L29/66825 ,  H01L29/66795

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture. The structure includes: at least one active gate structure; and a built-in temperature sensor adjacent to and on a same device level as the at least one active gate structure, the built-in temperature sensor further includes force lines and sensing lines.

公开(公告)号：US20240068879A1

公开(公告)日：2024-02-29

申请号：US17896823

申请日：2022-08-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhixing ZHAO ,  Yiching CHEN

IPC: G01K7/01

CPC classification number: G01K7/01

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture and operation. The structure includes: a semiconductor on insulator substrate; an insulator layer under the semiconductor on the insulator substrate; a handle substrate under insulator layer; a first well of a first dopant type in the handle substrate; a second well of a second dopant type in the handle substrate, adjacent to the first well; and a back-gate diode at a juncture of the first well and the second well.

公开(公告)号：US20230238439A1

公开(公告)日：2023-07-27

申请号：US18127206

申请日：2023-03-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Dirk UTESS ,  Zhixing ZHAO ,  Dominik M. KLEIMAIER ,  Irfan A. SAADAT ,  Florent RAVAUX

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/41775 ,  H01L29/401 ,  H01L29/7845 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.

公开(公告)号：US20230198474A1

公开(公告)日：2023-06-22

申请号：US17556528

申请日：2021-12-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yiching CHEN ,  Zhixing ZHAO

IPC: H03F1/32 ,  H03F3/213

CPC classification number: H03F1/3205 ,  H03F3/213

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a differential circuit with automatic parasitic neutralization and gain boost and methods of manufacture. The structure includes a plurality of auxiliary circuit devices with back-gate controls to perform a boost gain, and a differential pair of circuit devices which are connected to the auxiliary circuit devices.