公开(公告)号：US20240429208A1

公开(公告)日：2024-12-26

申请号：US18340230

申请日：2023-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Satyasuresh Vvss Choppalli ,  Rui Tze Toh ,  Mei Hui June Goh

IPC: H01L25/07 ,  H01L23/00 ,  H01L25/00

Abstract: Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions, a body region on a channel region between the source and drain regions, and a gate structure adjacent to and between the channel region and the dielectric material layers. An insulator layer is on the transistor opposite the dielectric material layers and includes an opening extending to the body region. Optionally, a semiconductor layer is at the bottom of the opening. A contact extends into the opening to the body region (or to the semiconductor layer thereon, if applicable).