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    POWER AMPLIFIER WITH BIASING SCHEME ENABLING HIGH POWER OPERATION
    2.
    发明申请
    POWER AMPLIFIER WITH BIASING SCHEME ENABLING HIGH POWER OPERATION 有权

    公开(公告)号：US20250112598A1

    公开(公告)日：2025-04-03

    申请号：US18479205

    申请日：2023-10-02

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Abdellatif Bellaouar ,  Shafiullah Syed

    IPC: H03F1/30 ,  H03F3/21

    Abstract: A disclosed structure includes a power amplifier and circuitry for implementing a biasing scheme that enables high power operation. The power amplifier includes parallel transistor chains connected to input and output transformers. Each chain includes series-connected first, second, and third n-type field effect transistors (NFETs) having front and back gates. The output transformer receives a variable positive power supply voltage generated using average power tracking. Front and back gates of each third NFET receive a positive bias voltage greater than or equal to the variable positive power supply voltage and a negative bias voltage, respectively. By negative back biasing the third NFETs, threshold voltages thereof are raised so a high positive bias voltage can be applied to the front gates to increase power output without violating reliability specifications. Optionally, by making the negative bias voltage temperature dependent, voltages at source regions of the third NFETs are held constant.

    STATIC RANDOM ACCESS MEMORY (SRAM) CELL WITH VARIABLE TOGGLE THRESHOLD VOLTAGE AND MEMORY CIRCUIT INCLUDING SRAM CELLS
    3.
    发明申请
    STATIC RANDOM ACCESS MEMORY (SRAM) CELL WITH VARIABLE TOGGLE THRESHOLD VOLTAGE AND MEMORY CIRCUIT INCLUDING SRAM CELLS 有权

    公开(公告)号：US20250078913A1

    公开(公告)日：2025-03-06

    申请号：US18459530

    申请日：2023-09-01

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Xuemei Hui ,  Shafiullah Syed ,  Qiao Yang ,  Wei Zhao

    IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

    Abstract: A static random access memory (SRAM) cell includes P-type and N-type transistors having secondary gates. A node connected to all secondary gates receives a write enable signal (WEN). A low WEN forward biases the P-type transistors and increases the toggle threshold voltage (Vtth) of the SRAM cell to avoid data switching during a read. A high WEN forward biases the N-type transistors and decreases Vtth during a write. The SRAM cell can be implemented using a fully depleted semiconductor-on-insulator technology, where the secondary gates include corresponding portions of a well region below. In this case, an array of SRAM cells can be above a single well region. Alternatively, the array can be sectioned into sub-arrays above different well regions and a decoder can output sub-array-specific WENs to the different well regions (e.g., with only one WEN being high at a given time to reduce capacitance).

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