公开(公告)号：US20230341888A1

公开(公告)日：2023-10-26

申请号：US17726171

申请日：2022-04-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Sunil Kumar ,  Shivraj G. Dharne ,  Mahbub Rashed

IPC: G06F1/10 ,  G06F15/78

CPC classification number: G06F1/10 ,  G06F15/7839

Abstract: An apparatus includes a series of pipeline stages that have logic components connected to supply output data to latch components, timing correction blocks connected to the latch components, and a memory component connected to supply a correction pattern to the timing correction blocks. The timing correction blocks have a buffer connected to a multiplexor. The correction pattern controls whether the multiplexor receives an adjusted clock signal through the buffer to control whether the timing correction blocks supply an unadjusted clock signal or the adjusted clock signal to the latch components.

公开(公告)号：US12050485B2

公开(公告)日：2024-07-30

申请号：US17726171

申请日：2022-04-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Sunil Kumar ,  Shivraj G. Dharne ,  Mahbub Rashed

IPC: G06F1/10 ,  G06F9/38 ,  G06F15/78

CPC classification number: G06F1/10 ,  G06F15/7839

Abstract: An apparatus includes a series of pipeline stages that have logic components connected to supply output data to latch components, timing correction blocks connected to the latch components, and a memory component connected to supply a correction pattern to the timing correction blocks. The timing correction blocks have a buffer connected to a multiplexor. The correction pattern controls whether the multiplexor receives an adjusted clock signal through the buffer to control whether the timing correction blocks supply an unadjusted clock signal or the adjusted clock signal to the latch components.