公开(公告)号：US12124699B2

公开(公告)日：2024-10-22

申请号：US18053948

申请日：2022-11-09

Applicant: Graphcore Limited

Inventor： Alan Alexander ,  Edward Andrews ,  Peter Hedinger

IPC: G06F3/06 ,  G06F9/30

CPC classification number: G06F3/0608 ,  G06F3/0659 ,  G06F3/067 ,  G06F9/30036 ,  G06F9/30109

Abstract: A new type of instruction and a control register for the new type of instruction are provided to handle data that may be misaligned in memory. A first part of data (which may be misaligned in memory) is loaded into a first set of registers by loading a first atom containing the first part of data into registers. The pack instruction is executed by an execution unit to place part of data (whose length and starting position are indicated by second and third values in a control register) from one set of registers into an identified location (identified by a first value in the control register) in another set of registers.

公开(公告)号：US11928523B2

公开(公告)日：2024-03-12

申请号：US17446681

申请日：2021-09-01

Applicant: Graphcore Limited

Inventor： Simon Knowles ,  Daniel John Pelham Wilkinson ,  Alan Alexander ,  Stephen Felix ,  Richard Osborne ,  David Lacey ,  Lars Paul Huse

IPC: G06F1/04 ,  G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F1/12

CPC classification number: G06F9/522 ,  G06F9/30087 ,  G06F9/3858 ,  G06F1/12

Abstract: A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.

公开(公告)号：US12112164B2

公开(公告)日：2024-10-08

申请号：US18176034

申请日：2023-02-28

Applicant: Graphcore Limited

Inventor： Alan Alexander ,  Simon Knowles ,  Godfrey Da Costa ,  Badreddine Noune

IPC: G06F9/30

CPC classification number: G06F9/30014 ,  G06F9/3013

Abstract: A processing device comprising a plurality of operand registers, wherein a first subset of the operand registers are configured to store state information for a plurality of bins, comprising a range of values and a bin count associated with each respective bin, wherein a second subset of the operand registers is configured to store a vector of floating-point values; and an execution unit configured to execute a first instruction taking the state information for the plurality of bins and the vector of floating-point values as operands, and in response to execution of the first instruction, for each of the floating-point values: identify based on an exponent of the respective floating-point value, each one of the plurality of bins for which the respective floating-point value falls within the associated range of values; and increment the bin count associated with the identified bins.

公开(公告)号：US11966740B2

公开(公告)日：2024-04-23

申请号：US17444788

申请日：2021-08-10

Applicant: Graphcore Limited

Inventor： Mrudula Gore ,  Alan Alexander

IPC: G06F9/30 ,  G06N3/02

CPC classification number: G06F9/3013 ,  G06F9/30025 ,  G06F9/30105 ,  G06N3/02

Abstract: A processor comprising: a register file comprising a group of operand registers for holding data values, each operand register being a fixed number of bits in length for holding a respective data value of that length; and processing logic comprising floating point logic for performing floating point operations on data values in the register file, the floating point logic is configured to process the fixed number of bits in the respective data value according to a floating point format comprising a set of mantissa bits and a set of exponent bits. The processing logic is operable to select between a plurality of different variants of the floating point format, at least some of the variants having a different size sets of mantissa bits and exponent bits relative to one another.