公开(公告)号：US11928523B2

公开(公告)日：2024-03-12

申请号：US17446681

申请日：2021-09-01

Applicant: Graphcore Limited

Inventor： Simon Knowles ,  Daniel John Pelham Wilkinson ,  Alan Alexander ,  Stephen Felix ,  Richard Osborne ,  David Lacey ,  Lars Paul Huse

IPC: G06F1/04 ,  G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F1/12

CPC classification number: G06F9/522 ,  G06F9/30087 ,  G06F9/3858 ,  G06F1/12

Abstract: A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.

公开(公告)号：US11907725B2

公开(公告)日：2024-02-20

申请号：US18164202

申请日：2023-02-03

Applicant: Graphcore Limited

Inventor： Richard Osborne ,  Matthew Fyles

IPC: G06F9/30 ,  G06F9/38 ,  G06N20/00 ,  G06F9/48 ,  G06F9/52 ,  G06F15/80 ,  G06N3/084 ,  H04L45/00

CPC classification number: G06F9/3885 ,  G06F9/3001 ,  G06F9/4881 ,  G06F9/522 ,  G06F15/80 ,  G06N3/084 ,  G06N20/00 ,  H04L45/00

Abstract: A computer comprising a plurality of processors, each of which are configured to perform operations on data during a compute phase for the computer and, following a pre-compiled synchronisation barrier, exchange data with at least one other of the processors during an exchange phase for the computer, wherein of the processors in the computer is indexed and the data exchange operations carried out by each processor in the exchange phase depend upon its index value.

公开(公告)号：US11449254B1

公开(公告)日：2022-09-20

申请号：US17024357

申请日：2020-09-17

Applicant: Graphcore Limited

Inventor： Richard Osborne ,  Chad Jarvis ,  Fabian Tschopp ,  Tim Hutt ,  Emmanuel Menage

IPC: G06F3/06 ,  G06F8/41 ,  G06N3/04

Abstract: A system and method for providing a set of data transfer instructions for converting one or more tensors between two different layouts. A first layout is used for storage of the data in host memory. A second layout is used for storage of the data in external memory accessible to a subsystem. The subsystem acts as a work accelerator to the host, and reads the external memory and processes the data read from the external memory. The first layout may be a logical representation of the tensor. The second layout is optimised for transfer to and processing by the subsystem. The data transfer instructions for converting between the two layouts are generated in dependence upon an analysis of the instructions to be executed by the subsystem.

公开(公告)号：US11599363B2

公开(公告)日：2023-03-07

申请号：US16840988

申请日：2020-04-06

Applicant: Graphcore Limited

Inventor： Richard Osborne ,  Matthew Fyles

IPC: G06F9/30 ,  G06F9/38 ,  G06N20/00 ,  G06F9/48 ,  G06F9/52 ,  G06F15/80 ,  G06N3/084

Abstract: A computer comprising a plurality of processors, each of which are configured to perform operations on data during a compute phase for the computer and, following a pre-compiled synchronisation barrier, exchange data with at least one other of the processors during an exchange phase for the computer, wherein of the processors in the computer is indexed and the data exchange operations carried out by each processor in the exchange phase depend upon its index value.