公开(公告)号：US12204961B2

公开(公告)日：2025-01-21

申请号：US18528086

申请日：2023-12-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： John Paul Strachan ,  Dejan S. Milojicic ,  Martin Foltin ,  Sai Rahul Chalamalasetti ,  Amit S. Sharma

IPC: G06J1/00 ,  G06F17/16

Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

公开(公告)号：US20240020155A1

公开(公告)日：2024-01-18

申请号：US18476690

申请日：2023-09-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S. Milojicic ,  Kimberly Keeton ,  Paolo Faraboschi ,  Cullen E. Bash

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/505 ,  G06F9/5044 ,  G06F9/5005 ,  G06F9/5055

Abstract: Systems and methods are provided for incorporating an optimized dispatcher with an FaaS infrastructure to permit and restrict access to resources. For example, the dispatcher may assign requests to “warm” resources and initiate a fault process if the resource is overloaded or a cache-miss is identified (e.g., by restarting or rebooting the resource). The warm instances or accelerators associated with the allocation size that are identified may be commensurate to the demand and help dynamically route requests to faster accelerators.

公开(公告)号：US11561607B2

公开(公告)日：2023-01-24

申请号：US17085805

申请日：2020-10-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Catherine Graves ,  Can Li ,  John Paul Strachan ,  Dejan S. Milojicic ,  Kimberly Keeton

IPC: G11C16/04 ,  G06F1/3296 ,  G11C13/00 ,  G06F1/3206 ,  G11C27/00

Abstract: Encoding of domain logic rules in an analog content addressable memory (aCAM) is disclosed. By encoding domain logic in an aCAM, rapid and flexible search capabilities are enabled, including the capability to search ranges of analog values, fuzzy match capabilities, and optimized parameter search capabilities. This is achieved with low latency by using only a small number of clock cycles at low power. A domain logic ruleset may be represented using various data structures such as decision trees, directed graphs, or the like. These representations can be converted to a table of values, where each table column can be directly mapped to a corresponding row of the aCAM.

公开(公告)号：US11294763B2

公开(公告)日：2022-04-05

申请号：US16115100

申请日：2018-08-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Catherine Graves ,  Dejan S. Milojicic ,  Paolo Faraboschi ,  Martin Foltin ,  Sergey Serebryakov

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52

Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.

公开(公告)号：US11182134B2

公开(公告)日：2021-11-23

申请号：US16799637

申请日：2020-02-24

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dejan S. Milojicic ,  Mehmet Kivanc Ozonat ,  Sergey Serebryakov

IPC: G06F8/35 ,  G06F9/445

Abstract: Systems and methods are provided for optimizing parameters of a system across an entire stack, including algorithms layer, toolchain layer, execution or runtime layer, and hardware layer. Results from the layer-specific optimization functions of each domain can be consolidated using one or more consolidation optimization functions to consolidate the layer-specific optimization results, capturing the relationship between the different layers of the stack. Continuous monitoring of the programming model during execution may be implemented and can enable the programming model to self-adjust based on real-time performance metrics. In this way, programmers and system administrators are relieved of the need for domain knowledge and are offered a systematic way for continuous optimization (rather than an ad hoc approach).

公开(公告)号：US10983831B2

公开(公告)日：2021-04-20

申请号：US16058506

申请日：2018-08-08

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dejan S. Milojicic ,  Derek Schumacher ,  Zhikui Wang

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F9/4401 ,  G06F11/22 ,  G06F9/54

Abstract: Examples relate to firmware-based provisioning of hardware resources. In some of the examples, firmware discovers and takes ownership of a hardware resource. At this stage, the firmware performs a test to verify the hardware resource. The firmware then assigns the hardware resource to an OS instance. At this stage, the firmware can suspend assigning further hardware resources to the OS instance in response to a satisfied notification from the OS instance.

公开(公告)号：US20200050493A1

公开(公告)日：2020-02-13

申请号：US16058506

申请日：2018-08-08

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dejan S. Milojicic ,  Derek Schumacher ,  Zhikui Wang

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F9/4401 ,  G06F11/22

Abstract: Examples relate to firmware-based provisioning of hardware resources. In some of the examples, firmware discovers and takes ownership of a hardware resource. At this stage, the firmware performs a test to verify the hardware resource. The firmware then assigns the hardware resource to an OS instance. At this stage, the firmware can suspend assigning further hardware resources to the OS instance in response to a satisfied notification from the OS instance.

公开(公告)号：US10545909B2

公开(公告)日：2020-01-28

申请号：US15305405

申请日：2014-04-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Yuan Chen ,  Daniel Juergen Gmach ,  Dejan S. Milojicic ,  Vanish Talwar ,  Zhikui Wang

IPC: G06F15/167 ,  H04L29/08

Abstract: A system management command is stored in a management partition of a global memory by a first node of a multi-node computing system. The global memory is shared by each node of the multi-node computing system. In response to an indication to access the management partition, the system management command is accessed from the management partition by a second node of the multi-node computing system. The system management command is executed by the second node. Executing the system management command includes managing the second node.

公开(公告)号：US20190332538A1

公开(公告)日：2019-10-31

申请号：US15967596

申请日：2018-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S. Milojicic ,  Keith Packard ,  Michael S. Woodacre ,  Andrew R. Wheeler

IPC: G06F12/0837

Abstract: Systems and methods for dynamically modifying coherence domains are discussed herein. In various embodiments, a hardware controller may be provided that is configured to automatically recognize application behavior and dynamically reconfigure coherence domains in hardware and software to tradeoff performance for reliability and scalability. Modifying the coherence domains may comprise repartitioning the system based on cache coherence independently of one or more software layers of the system. Memory-driven algorithms may be invoked to determine one or more dynamic coherence domain operations to implement. In some embodiments, declarative policy statements may be received from a user via one or more interfaces associated with the controller. The controller may be configured to dynamically adjust cache coherence policy based on the declarative policy statements received from the user.

公开(公告)号：US10261882B2

公开(公告)日：2019-04-16

申请号：US15114086

申请日：2014-01-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S. Milojicic ,  Yuan Chen ,  Daniel J. Gmach ,  Vanish Talwar ,  Zhikui Wang

IPC: G06F11/30 ,  G06F1/3287 ,  G06F9/50 ,  G06F1/3215 ,  G06F1/3296 ,  G06F11/34

Abstract: A system comprises a plurality of functional units powered via a power source. The system further comprises a first functional unit and a second functional unit, wherein the second functional unit is to promote the first functional unit to a management unit based on a management requirement of the system. The management unit is to administrate operations of the system. Once the first functional unit is promoted, the management unit is isolated from the functional units that were not promoted via a virtual network path and a power management unit.