-
公开(公告)号：US12272401B2
公开(公告)日：2025-04-08
申请号：US18308990
申请日：2023-04-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Ron M. Roth , Luca Buonanno , Giacomo Pedretti , Catherine Graves
Abstract: Systems and methods are provided for implementing a low power and area ternary content addressable memory (TCAM). An example of a TCAM comprises a match line, and a plurality of TCAM cells connected along the match line. Each TCAM cell stores a state of a threshold value. The TCAM cells are configured to pull down a signal over the match line in response to inequality between an input search and the threshold value. The plurality of TCAM cells comprises a number of TCAM cells that is less than the threshold value. The input values can be encoded according to a first encoding scheme and the threshold value can be encoded according to one of a second and a third encoding scheme based on an inequality check mapped to the plurality of TCAM cells.
-
公开(公告)号：US11763888B1
公开(公告)日：2023-09-19
申请号：US17872923
申请日：2022-07-25
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Giacomo Pedretti , John Moon , Pedro Henrique Rocha Bruel , Catherine Graves
CPC classification number: G11C15/04 , G11C7/16 , G11C16/102 , G11C16/3404
Abstract: Systems and methods provide new circuits that increase aCAM precision by leveraging the concept of range segmenting to representationally store an analog voltage range across multiple aCAM cells/sub-circuits (here the representationally stored analog voltage range may correspond to a word entry). In this way, a circuit of the presently disclosed technology can increase precision (e.g., the number of programmable levels that can be used to store a word entry and/or the number of programmable levels that an input signal can be search against) linearly with each aCAM cell/sub-circuit added to the circuit. Accordingly, circuits of the presently disclosed technology can be used to carry out more complex computations than conventional aCAMs—and thus can be used in a wider range of computational applications.
-
公开(公告)号：US20250095736A1
公开(公告)日：2025-03-20
申请号：US18469457
申请日：2023-09-18
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Giacomo Pedretti , Catherine Graves , John Paul Strachan
IPC: G11C15/04
Abstract: A technique for compressing an analog content addressable memory (CAM) array is provided. Random input data is applied to the analog CAM array, and an average measure of similarity is calculated for each output row of the analog CAM array. Rows of the analog CAM array that have measures of similarity that are close to each other can be eliminated, such as by removing similar rows or merging together similar rows. Thus, the analog CAM array size can be reduced without a loss in accuracy of a model stored on the analog CAM array.
-
公开(公告)号：US12205659B2
公开(公告)日：2025-01-21
申请号：US18483448
申请日：2023-10-09
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Giacomo Pedretti , John Paul Strachan , Catherine Graves
Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.
-
公开(公告)号：US12106805B2
公开(公告)日：2024-10-01
申请号：US17872882
申请日：2022-07-25
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Tobias Frederic Ziegler , Ron M. Roth , Giacomo Pedretti , Luca Buonanno , Pedro Henrique Rocha Bruel , Catherine Graves
IPC: G11C15/04 , G11C16/10 , G11C16/12 , H03K19/017
CPC classification number: G11C15/04 , G11C16/102 , G11C16/12 , H03K19/01742
Abstract: Examples increase precision for aCAMs by converting an input signal (x) received by a circuit into a first analog voltage signal (V(xMSB)) representing the most significant bits of the input signal (x) and a second analog voltage signal (V(xLSB)) representing the least significant bits of the input signal (x). By dividing the input signal (x) bit-wise into the first analog voltage signal (V(xMSB)) and the second analog voltage signal (V(xLSB)), the circuit can utilize aCAM sub-circuits implementing a combination of Boolean operations to search the input signal (x) against 22*M programmable levels, where “M” represents the number of programmable bits for each aCAM sub-circuit. Thus, using similar circuit hardware, example circuits square the number of programmable levels of conventional aCAMs (which generally only have 2M programmable levels). Accordingly, examples provide new aCAMs that can carry out more complex computations than conventional aCAMs of comparable cost, size, and power consumption.
-
Patent Agency Ranking
公开(公告)号：US20240047002A1
公开(公告)日：2024-02-08
申请号：US18483448
申请日：2023-10-09
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Giacomo Pedretti , John Paul Strachan , Catherine Graves
CPC classification number: G11C27/005 , G11C15/046
Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.
-
公开(公告)号：US12277971B2
公开(公告)日：2025-04-15
申请号：US18420978
申请日：2024-01-24
Applicant: Hewlett Packard Enterprise Development LP
Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells, applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause and updating one or more variables within the interpretation if at least one clause is violated.
-
公开(公告)号：US12254924B2
公开(公告)日：2025-03-18
申请号：US17876471
申请日：2022-07-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Giacomo Pedretti , Catherine Graves , Sergey Serebryakov , John Paul Strachan
Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for providing a differentiable content addressable memory (aCAM) that implements an analog input analog storage and analog output learning memory. The analog output of the differentiable CAM can provide input to a learning algorithm, which may compute the gradients in comparison to historic values and reduce data inaccuracies and power consumption.
-
公开(公告)号：US20240184479A1
公开(公告)日：2024-06-06
申请号：US18418825
申请日：2024-01-22
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Giacomo Pedretti , John Paul Strachan , Thomas Maurits M. Van Vaerenbergh , Catherine E. Graves
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673 , G06N3/063
Abstract: A system for facilitating an enhanced k-SAT solver is provided. The system can include a set of analog content addressable memory (aCAM) modules that can represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression. The system can also include a set of data lines that can provide input candidate values to the set of aCAM modules. A controller of the system can program the set of aCAM modules with respective analog values to represent the expression. The system can also include sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules. The controller can then iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.
-
公开(公告)号：US11881261B2
公开(公告)日：2024-01-23
申请号：US17555260
申请日：2021-12-17
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Catherine Graves , Giacomo Pedretti , Sergey Serebryakov , John Paul Strachan
CPC classification number: G11C13/004 , G06N7/01 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C15/04
Abstract: Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.
-
-
-
-
-
-
-
-
-
Search Results
20
records
(took 0.019 seconds)
