公开(公告)号：US20250054547A1

公开(公告)日：2025-02-13

申请号：US18447776

申请日：2023-08-10

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Giacomo Pedretti ,  Todd Richmond ,  Thomas Van Vaerenbergh

IPC: G11C15/04 ,  H03K19/21

Abstract: Examples of the presently disclosed technology provide CAM-based circuits specially constructed to implement Boolean satisfiability problems involving k-XOR-SAT clauses. With the strategic addition of auxiliary counting and logic circuits that evaluate match line voltage outputs of a CAM at k discrete times in order to determine whether a counted number of matches returned by a match line satisfies a pre-determine parity condition—where k represents a number of literals of a k-XOR-SAT clause of a Boolean satisfiability problem—a circuit of the present technology can leverage a common CAM (i.e., the same CAM) to implement the k-XOR-SAT clause and k-SAT clauses. Accordingly, this extremely versatile circuit can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT hybrid problems in less time, and with less hardware and power consumption than existing hardware accelerators.