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    Computational accuracy in a crossbar array
    1.
    发明授权
    Computational accuracy in a crossbar array 有权

    公开(公告)号：US10482940B2

    公开(公告)日：2019-11-19

    申请号：US16062578

    申请日：2015-12-17

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Miao Hu ,  John Paul Strachan ,  Zhiyong Li ,  Stanley Williams

    IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00

    Abstract: Example implementations of the present disclosure relate to improved computational accuracy in a crossbar array. An example system may include a crossbar array, having a plurality of memory elements at junctions, usable in performance of computations. The example system may further include a calculate engine to calculate ideal conductance of memory elements at a plurality of junctions of the crossbar array and a determine engine to determine conductance of the memory elements at the plurality of junctions of the crossbar array. An adjust engine of the example system may be used to adjust conductance of at least one memory element to improve computational accuracy by reduction of a difference between the ideal conductance and the determined conductance of the at least one memory element.

    Asymmetrically selecting memory elements
    2.
    发明授权
    Asymmetrically selecting memory elements 有权

    公开(公告)号：US09934849B2

    公开(公告)日：2018-04-03

    申请号：US15320779

    申请日：2014-07-25

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Kyung Min Kim ,  Jianhua Yang ,  Zhiyong Li

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/003 ,  G11C2013/0073 ,  G11C2213/72

    Abstract: A system for asymmetrically selecting a memory element is described. The system includes a number of memory cells in a crossbar array. Each memory cell includes a memory element to store information. The memory element is defined as an intersection between a column electrode and a row electrode of the crossbar array. Each memory cell also includes a selector to select a target memory element by relaying a first selecting voltage to a column electrode that corresponds to the target memory element and relaying a second selecting voltage to a row electrode that corresponds to the target memory element. The system also includes a controller to pass a first standing voltage to column electrodes of the crossbar array and to pass a second standing voltage to row electrodes of the crossbar array. The first standing voltage is different than the second standing voltage.

    MEMORY DEVICES WITH VOLATILE AND NON-VOLATILE BEHAVIOR
    5.
    发明申请
    MEMORY DEVICES WITH VOLATILE AND NON-VOLATILE BEHAVIOR 审中-公开

    公开(公告)号：US20190043562A1

    公开(公告)日：2019-02-07

    申请号：US16072575

    申请日：2016-02-12

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Zhiyong Li ,  Lu Zhang ,  Minxian Zhang

    IPC: G11C11/54 ,  G11C11/56 ,  G11C5/02 ,  G06N3/063

    Abstract: An example device in accordance with an aspect of the present disclosure includes an active oxide layer to form and dissipate a conductive bridge. The conductive bridge is to dissipate spontaneously within a relaxation time to enable the memory device to self-refresh according to volatile behavior in response to the input voltage being below a threshold corresponding to disregarding sneak current and noise of a crossbar array in which the memory device is to operate. The conductive bridge is to persist beyond the relaxation time to enable the memory device to retain programming for neuromorphic computing training according to non-volatile behavior of the memory device in response to the input voltage not being below the threshold.

    Linear transformation accelerators
    10.
    发明授权
    Linear transformation accelerators 有权

    公开(公告)号：US10529418B2

    公开(公告)日：2020-01-07

    申请号：US16079998

    申请日：2016-02-19

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Miao Hu ,  John Paul Strachan ,  Zhiyong Li ,  R. Stanley Williams

    IPC: G11C13/00 ,  G11C11/56

    Abstract: Examples herein relate to linear transformation accelerators. An example linear transformation accelerator may include a crossbar array programmed to calculate a linear transformation. The crossbar array has a plurality of words lines, a plurality of bit lines, and a memory cell coupled between each unique combination of one word line and one bit line, where the memory cells are programmed according to a linear transformation matrix. The plurality of word lines are to receive an input vector, and the plurality of bit lines are to output an output vector representing a linear transformation of the input vector.

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