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    Determining whether a right to use memory modules in a reliability mode has been acquired
    1.
    发明授权
    Determining whether a right to use memory modules in a reliability mode has been acquired 有权
    确定是否获得了以可靠性模式使用内存模块的权利

    公开(公告)号：US08812915B2

    公开(公告)日：2014-08-19

    申请号：US13628659

    申请日：2012-09-27

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Lidia Warnes ,  Russ W. Herrell ,  Blaine D. Gaither

    IPC: G06F11/00

    CPC classification number: G06F11/1008

    Abstract: Examples disclosed herein relate to determining whether a right to use memory modules in a reliability mode has been acquired. Examples include determining whether the right to use a plurality of memory modules in a reliability mode has been acquired, if a performance mode is selected for operation of the plurality of memory modules.

    Abstract translation: 本文公开的示例涉及确定是否已经获得了以可靠性模式使用存储器模块的权利。 例如，如果选择了用于多个存储器模块的操作的性能模式，则确定是否已经获取了以可靠性模式使用多个存储器模块的权利。

    DETERMINING WHETHER A RIGHT TO USE MEMORY MODULES IN A RELIABILITY MODE HAS BEEN ACQUIRED
    3.
    发明申请
    DETERMINING WHETHER A RIGHT TO USE MEMORY MODULES IN A RELIABILITY MODE HAS BEEN ACQUIRED 有权
    确定在可靠性模式下使用存储器模块的权限已被获取

    公开(公告)号：US20140089726A1

    公开(公告)日：2014-03-27

    申请号：US13628659

    申请日：2012-09-27

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Lidia Warnes ,  Russ W. Herrell ,  Blaine D. Gaither

    IPC: G06F11/26

    CPC classification number: G06F11/1008

    Abstract: Examples disclosed herein relate to determining whether a right to use memory modules in a reliability mode has been acquired. Examples include determining whether the right to use a plurality of memory modules in a reliability mode has been acquired, if a performance mode is selected for operation of the plurality of memory modules.

    Abstract translation: 本文公开的示例涉及确定是否已经获得了以可靠性模式使用存储器模块的权利。 例如，如果选择了用于多个存储器模块的操作的性能模式，则确定是否已经获取了以可靠性模式使用多个存储器模块的权利。

    IMPLEMENTING COHERENCY WITH REFLECTIVE MEMORY
    4.
    发明申请
    IMPLEMENTING COHERENCY WITH REFLECTIVE MEMORY 有权
    用反射记忆实现相关性

    公开(公告)号：US20160026576A1

    公开(公告)日：2016-01-28

    申请号：US14763943

    申请日：2013-03-28

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Gregg B. Lesartre ,  Robert J. Brooks ,  Blaine D. Gaither

    IPC: G06F12/08

    CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0837 ,  G06F2212/1032 ,  G06F2212/281

    Abstract: Techniques for updating data in a reflective memory region of a first memory device are described herein. In one example, a method for updating data in a reflective memory region of a first memory device includes receiving an indication that data is to be flushed from a cache device to the first memory device. The method also includes detecting a memory address corresponding to the data is within the reflective memory region of the first memory device and sending data from the cache device to the first memory device with a flush operation. Additionally, the method includes determining that the data received by the first memory device is modified data. Furthermore, the method includes sending the modified data to a second memory device in a second computing system.

    Abstract translation: 本文描述了用于更新第一存储器件的反射存储器区域中的数据的技术。 在一个示例中，用于更新第一存储器设备的反射存储器区域中的数据的方法包括接收将数据从缓存设备刷新到第一存储器设备的指示。 该方法还包括检测与第一存储器件的反射存储器区域内的数据相对应的存储器地址，并且利用刷新操作将数据从高速缓存器件发送到第一存储器件。 此外，该方法包括确定由第一存储器设备接收的数据是修改的数据。 此外，该方法包括将修改的数据发送到第二计算系统中的第二存储器设备。

    Cache and method for cache bypass functionality
    5.
    发明授权
    Cache and method for cache bypass functionality 有权
    缓存和缓存旁路功能的方法

    公开(公告)号：US09405696B2

    公开(公告)日：2016-08-02

    申请号：US14165947

    申请日：2014-01-28

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Blaine D. Gaither ,  Patrick Knebel

    IPC: G06F12/08

    CPC classification number: G06F12/0888 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0897

    Abstract: A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.

    Abstract translation: 提供了用于将处理器与主存储器可操作地耦合的高速缓存。 高速缓存包括与高速缓冲存储器可操作地耦合的高速缓冲存储器和高速缓存控制器。 缓存控制器被配置为接收由高速缓冲存储器或主存储器满足的存储器请求。 此外，高速缓存控制器被配置为处理高速缓存活动信息以使至少一个存储器请求绕过高速缓冲存储器。

    SPLIT MODE ADDRESSING A PERSISTENT MEMORY
    6.
    发明申请
    SPLIT MODE ADDRESSING A PERSISTENT MEMORY 审中-公开
    分离模式寻址一个持续记忆

    公开(公告)号：US20160041928A1

    公开(公告)日：2016-02-11

    申请号：US14780392

    申请日：2013-03-28

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Gregg B. Lesartre ,  Blaine D. Gaither ,  Dale C. Morris ,  Carey Huscroft ,  Russ W. Herrell

    IPC: G06F12/14

    CPC classification number: G06F12/1408 ,  G06F12/0246 ,  G06F12/1483 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/7201

    Abstract: A system and method for addressing split modes of persistent memory are described herein. The system includes a non-volatile memory comprising regions of memory, each region comprising a range of memory address spaces. The system also includes a memory controller (MC) to control access to the non-volatile memory. The system further includes a device to track a mode of each region of memory and to define the mode of each region of memory. The mode is a functional use model.

    Abstract translation: 本文描述了用于寻址持久存储器的分离模式的系统和方法。 该系统包括包括存储器区域的非易失性存储器，每个区域包括一定范围的存储器地址空间。 该系统还包括用于控制对非易失性存储器的访问的存储器控​​制器（MC）。 该系统还包括跟踪每个存储器区域的模式并定义每个存储器区域的模式的设备。 该模式是功能使用模式。

    Implementing coherency with reflective memory
    7.
    发明授权
    Implementing coherency with reflective memory 有权
    用反射记忆实现一致性

    公开(公告)号：US09575898B2

    公开(公告)日：2017-02-21

    申请号：US14763943

    申请日：2013-03-28

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Gregg B. Lesartre ,  Robert J. Brooks ,  Blaine D. Gaither

    IPC: G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0837 ,  G06F2212/1032 ,  G06F2212/281

    Abstract: Techniques for updating data in a reflective memory region of a first memory device are described herein. In one example, a method for updating data in a reflective memory region of a first memory device includes receiving an indication that data is to be flushed from a cache device to the first memory device. The method also includes detecting a memory address corresponding to the data is within the reflective memory region of the first memory device and sending data from the cache device to the first memory device with a flush operation. Additionally, the method includes determining that the data received by the first memory device is modified data. Furthermore, the method includes sending the modified data to a second memory device in a second computing system.

    Abstract translation: 本文描述了用于更新第一存储器件的反射存储器区域中的数据的技术。 在一个示例中，用于更新第一存储器设备的反射存储器区域中的数据的方法包括接收将数据从缓存设备刷新到第一存储器设备的指示。 该方法还包括检测与第一存储器件的反射存储器区域内的数据相对应的存储器地址，并且利用刷新操作将数据从高速缓存器件发送到第一存储器件。 此外，该方法包括确定由第一存储器设备接收的数据是修改的数据。 此外，该方法包括将修改的数据发送到第二计算系统中的第二存储器设备。

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