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公开(公告)号：US20120168220A1
公开(公告)日：2012-07-05
申请号：US13281264
申请日：2011-10-25
Applicant: Han Ul Lee , Byung Bae SEO , Chang Sup RYU , Yong Sam LEE
Inventor： Han Ul Lee , Byung Bae SEO , Chang Sup RYU , Yong Sam LEE
CPC classification number: H05K3/429 , H05K2201/09454 , H05K2201/09563 , H05K2201/096 , H05K2203/107 , H05K2203/1572 , Y10T29/49165
Abstract: Disclosed herein are a multi-layer printed circuit board and a method of manufacturing the same. In the multi-layer printed circuit board and the method of manufacturing the same, circuit layers formed in a plurality of insulating layers are electrically interconnected through vias formed in a lump, thereby making it possible to secure bonding reliability of an interlayer circuit layer and more stably secure performance of the printed circuit board. In addition, since a stacked type via structure may be implemented by performing a via hole drilling process, a desmear process, and a copper plating process only one time after an insulating layer and an circuit layer are stacked, a manufacturing process, a manufacturing time, and manufacturing costs of the stacked type via structure may be reduced.
Abstract translation: 这里公开了多层印刷电路板及其制造方法。 在多层印刷电路板及其制造方法中，形成在多个绝缘层中的电路层通过一体形成的通孔电连接，从而可以确保层间电路层的结合可靠性和更多 稳定地确保印刷电路板的性能。 此外，由于堆叠型通孔结构可以通过在绝缘层和电路层堆叠后一次进行通孔钻孔工艺，去污工艺和镀铜处理来实现，制造工艺，制造时间 ，并且可以减小层叠型通孔结构的制造成本。
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公开(公告)号：US09018539B2
公开(公告)日：2015-04-28
申请号：US13487909
申请日：2012-06-04
Applicant: Han Ul Lee
Inventor： Han Ul Lee
CPC classification number: H05K1/115 , H05K3/0035 , H05K2201/09845 , H05K2203/1476 , Y10T29/49126
Abstract: The present invention relates to a printed circuit board including: a first circuit pattern formed on a first insulator; a second insulator formed on the first insulator; a second circuit pattern having a pad of which a portion is embedded in the second insulator and a via which penetrates the second insulator to electrically connect the first circuit pattern and the pad; and a third circuit pattern formed on the second insulator, and it is possible to reduce a size of the via without increasing an aspect ratio.
Abstract translation: 印刷电路板技术领域本发明涉及一种印刷电路板，包括：形成在第一绝缘体上的第一电路图案; 形成在第一绝缘体上的第二绝缘体; 第二电路图案，其具有嵌入第二绝缘体中的一部分的焊盘和穿过第二绝缘体以使第一电路图案和焊盘电连接的通孔; 以及形成在第二绝缘体上的第三电路图案，并且可以减小通孔的尺寸而不增加纵横比。
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公开(公告)号：US20130146349A1
公开(公告)日：2013-06-13
申请号：US13487909
申请日：2012-06-04
Applicant: Han Ul Lee
Inventor： Han Ul Lee
CPC classification number: H05K1/115 , H05K3/0035 , H05K2201/09845 , H05K2203/1476 , Y10T29/49126
Abstract: The present invention relates to a printed circuit board including: a first circuit pattern formed on a first insulator; a second insulator formed on the first insulator; a second circuit pattern having a pad of which a portion is embedded in the second insulator and a via which penetrates the second insulator to electrically connect the first circuit pattern and the pad; and a third circuit pattern formed on the second insulator, and it is possible to reduce a size of the via without increasing an aspect ratio.
Abstract translation: 印刷电路板技术领域本发明涉及一种印刷电路板，包括：形成在第一绝缘体上的第一电路图案; 形成在第一绝缘体上的第二绝缘体; 第二电路图案，其具有嵌入第二绝缘体中的一部分的焊盘和穿过第二绝缘体以电连接第一电路图案和焊盘的通孔; 以及形成在第二绝缘体上的第三电路图案，并且可以减小通孔的尺寸而不增加纵横比。
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