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    Low permeability hose system
    1.
    发明授权
    Low permeability hose system 有权
    低渗透软管系统

    公开(公告)号：US07857010B1

    公开(公告)日：2010-12-28

    申请号：US11615599

    申请日：2006-12-22

    Applicant: Howard L. Davidson

    Inventor： Howard L. Davidson

    IPC: F16L11/00

    CPC classification number: F16L11/12 ,  F16L2011/047 ,  Y10S138/10

    Abstract: A low permeability hose system for providing an impermeable length of tube to transfer fluids that is flexible. The low permeability hose system generally includes a hose defining a fluid passage and an impermeable layer attached to the exterior surface of the hose. The impermeable layer is comprised of an aluminum coated heat sealable film that is impermeable to both liquids and gases. A protective layer may be attached to the impermeable layer to protect the impermeable layer from damage.

    Abstract translation: 一种低渗透性软管系统，用于提供不透水长度的管以传输柔性的流体。 低渗透性软管系统通常包括限定流体通道的软管和附接到软管的外表面的不可渗透层。 不透水层由不透液体和气体的铝涂层可热封膜组成。 保护层可以附接到不渗透层以保护不渗透层免受损坏。

    Electro-desorption compressor
    2.
    发明授权
    Electro-desorption compressor 失效

    公开(公告)号：US06502419B2

    公开(公告)日：2003-01-07

    申请号：US09834080

    申请日：2001-04-12

    Applicant: Dennis M. Pfister ,  Charles M. Byrd ,  Howard L. Davidson

    Inventor： Dennis M. Pfister ,  Charles M. Byrd ,  Howard L. Davidson

    IPC: F25B3300

    CPC classification number: B82Y30/00 ,  F04B35/00 ,  F04B37/02 ,  F25B17/08 ,  F25B35/04 ,  Y10S977/734 ,  Y10S977/742 ,  Y10S977/842

    Abstract: A electro-desorption compression system according to the present invention comprises an enclosure which includes first and second spaced-apart electrical conductors, a sorbent which is positioned in the enclosure between the first and second conductors, a sorbate which is capable of combining with the sorbent in an adsorption reaction to form a sorbate/sorbent compound, a power supply which is connected to the first and second conductors and which generates an electrical current that is conducted through the sorbate/sorbent compound to desorb the sorbate from the sorbent in a desorption reaction, and a pressure chamber which is connected to the enclosure and which receives the sorbate from the enclosure during the desorption reaction and releases the sorbate into the enclosure during the adsorption reaction. The adsorption and desorption reactions are repeated to cycle the sorbate between a relatively low pressure state during the adsorption reaction and a relatively high pressure state during the desorption reaction. Furthermore, the desorption reaction is substantially non-thermal.

    Digital optical power modulator
    5.
    发明授权
    Digital optical power modulator 失效
    数字光功率调制器

    公开(公告)号：US5822108A

    公开(公告)日：1998-10-13

    申请号：US879507

    申请日：1997-06-20

    Applicant: Howard L. Davidson

    Inventor： Howard L. Davidson

    IPC: G02F1/01 ,  G02F7/00 ,  G02F1/29

    CPC classification number: G02F1/01 ,  G02F7/00

    Abstract: An integrated digital light modulator. In one embodiment, a light beam is split into a set of binary weighted beams which are then individually switched on or off by an optical switch. The weighted beams which are conveyed by the optical switches are then recombined to produce a modulated beam. In this manner, a fast inexpensive integrated digital light modulator may be advantageously obtained. Broadly speaking, the present invention contemplates a digital optical power modulator that comprises a binary power divider and an optical modulator. The binary power divider is configured to receive an input light beam and split it into a set of weighted beams. The optical powers of the weighted beams are related in that the ratio of the optical powers of any two weighted beams is substantially an integer power of two. The optical modulator receives the set of weighted beams from the binary power divider and receives a digital signal. The optical modulator is configured to convey weighted beams that correspond to asserted bits in the digital signal. The present invention may further include an optical combiner coupled to receive the weighted beams from the optical modulator and configured to combine the weighted beams to produce a modulated beam having a discrete optical power. A lookup table may be included to convert a desired digital power value into the digital signal provided to the optical modulator.

    Abstract translation: 集成数字光调制器。 在一个实施例中，光束被分割成一组二进制加权光束，然后通过光学开关单独地接通或关闭光束。 然后将由光开关传送的加权光束重新组合以产生调制光束。 以这种方式，可以有利地获得快速廉价的集成数字光调制器。 广义而言，本发明考虑了一种包括二进制功率分配器和光调制器的数字光功率调制器。 二进制功率分配器被配置为接收输入光束并将其分成一组加权波束。 加权光束的光功率的关联在于，任何两个加权光束的光功率的比率基本上是2的整数倍。 光调制器从二进制功率分配器接收一组加权波束并接收数字信号。 光调制器被配置为传送对应于数字信号中的断言位的加权波束。 本发明还可以包括光学组合器，其被耦合以从光学调制器接收加权光束并且被配置为组合加权光束以产生具有分立光焦度的调制光束。 可以包括查找表以将期望的数字功率值转换为提供给光学调制器的数字信号。

    Low inductance termination resistor arrays
    7.
    发明授权
    Low inductance termination resistor arrays 失效
    低电感终端电阻阵列

    公开(公告)号：US5661450A

    公开(公告)日：1997-08-26

    申请号：US560206

    申请日：1995-11-21

    Applicant: Howard L. Davidson

    Inventor： Howard L. Davidson

    IPC: H01C1/14 ,  H01C1/16 ,  H01C10/46 ,  H01L1/01

    CPC classification number: H04L25/0298 ,  H01C1/14 ,  H01C1/16 ,  H01C10/46 ,  Y10T29/49099

    Abstract: An array of termination resistors has symmetrical geometry producing essentially no net magnetic field and a resultant low inductance is fabricated on a substrate as disk resistors. Conductive through vias are formed in the substrate in an array pattern defining what will be resistor first and second contacts. Each disk resistor has one first contact located at the resistor disk center, and preferably four second contacts located symmetrically about the resistor disk and shared by four adjacent disk resistors. For each resistor, a annular-shaped disk of resistive material is fabricated on a first surface of the substrate, such that a central opening in the disk overlies at least the upper surface of a first contact via. The disk geometry and material determines its resistance. Next, a layer of conductive material is formed over the first surface of the substrate to cover at least the periphery of each disk, and to fill the central opening in each disk. This conductive material electrically couples at least the periphery of each resistive disk with each second contact via to define V.sub.T nodes, and also separately electrically couples the disk center to the underlying first contact via. Solder balls at the lower surface of each via provide an array of first and second contacts for each resistor for attaching the substrate to a printed wiring board or other substrate. An array may include hundreds of termination resistors having substantially real impedances in the range of 50 .OMEGA. to 100 .OMEGA. at frequencies up to about 12 GHz.

    Abstract translation: 终端电阻器阵列具有基本上不产生净磁场的对称几何形状，并且在基板上制造作为圆盘电阻器的合成低电感。 通过通孔的导电以阵列图案形成在衬底中，该阵列图形限定了将是电阻器第一和第二接触的部件。 每个盘式电阻器具有位于电阻器盘中心处的一个第一触点，并且优选地四个位于电阻器盘对称并且由四个相邻的磁盘电阻器共享的四个第二触点。 对于每个电阻器，在衬底的第一表面上制造电阻材料的环形盘，使得盘中的中心开口至少覆盖第一接触通孔的上表面。 磁盘几何和材料决定其电阻。 接下来，在基板的第一表面上形成导电材料层，以覆盖至少每个盘的周边，并填充每个盘中的中心开口。 该导电材料至少将每个电阻盘的周边与每个第二接触通孔电耦合以限定VT节点，并且还将盘中心分别电耦合到下面的第一接触通孔。 在每个通孔的下表面处的焊球提供用于每个电阻器的第一和第二触点的阵列，用于将衬底附接到印刷线路板或其它衬底。 在高达约12GHz的频率下，阵列可以包括数百个终端电阻器，其具有基本上实际阻抗在50欧姆到100欧姆的范围内。

    Method and apparatus for bit synchronization in optical communication and networking systems
    9.
    发明授权
    Method and apparatus for bit synchronization in optical communication and networking systems 有权
    光通信和网络系统中位同步的方法和装置

    公开(公告)号：US06437889B2

    公开(公告)日：2002-08-20

    申请号：US09827836

    申请日：2001-04-05

    Applicant: Howard L. Davidson

    Inventor： Howard L. Davidson

    IPC: H04J1408

    CPC classification number: H04L7/0075 ,  H04J14/08 ,  H04L7/0037 ,  H04L7/10

    Abstract: An apparatus and method are provided for bit synchronization in an optical time division multiplexed communication system. The apparatus is couplable to an optical gate, such as an optical demultiplexer. The apparatus includes a programmable optical delay line couplable to an input clock; an optical synchronizer coupled to the programmable optical delay line and couplable to the optical gate; and a processor coupled to the programmable optical delay line and to the optical synchronizer. The processor includes program instructions to track bit synchronization between a clock pulse and a selected data bit during a communication session; and when a bit tracking range is approaching a predetermined limit, the processor having further instructions to interrupt the communication session, return the bit tracking range to a zero offset and correspondingly adjust a programmable delay, and resume the communication session.

    Abstract translation: 提供了一种用于光时分复用通信系统中的位同步的装置和方法。 该装置可耦合到光栅，例如光解复用器。 该装置包括可耦合到输入时钟的可编程光学延迟线; 耦合到所述可编程光学延迟线并且可耦合到所述光学门的光学同步器; 以及耦合到可编程光学延迟线和光学同步器的处理器。 处理器包括用于在通信会话期间跟踪时钟脉冲和所选数据位之间的位同步的程序指令; 并且当位跟踪范围接近预定限制时，处理器具有中断通信会话的进一步指令，将比特追踪范围返回到零偏移并相应地调整可编程延迟，并恢复通信会话。

    Sub-package bypass capacitor mounting for an array packaged integrated circuit
    10.
    发明授权
    Sub-package bypass capacitor mounting for an array packaged integrated circuit 有权
    用于阵列封装集成电路的子封装旁路电容器安装

    公开(公告)号：US06400576B1

    公开(公告)日：2002-06-04

    申请号：US09286250

    申请日：1999-04-05

    Applicant: Howard L. Davidson

    Inventor： Howard L. Davidson

    IPC: H05K702

    CPC classification number: H01L23/66 ,  H01L23/642 ,  H01L25/162 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01057 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/112 ,  H05K2201/10325 ,  H05K2201/10545 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: Switching noise within an LGA-packaged or PGA-packaged IC Vdd and IC Vss nodes is reduced by spreading the electrical current in the bypass path to reduce the effective current loop area, and thus reduce the energy stored in the magnetic field surrounding the current path. This result is achieved by minimizing the horizontal components of the linkage paths between the IC nodes to be bypassed and the bypass capacitor. Since effective inductance Leff seen by the bypass capacitor is proportional to magnetic energy, Leff is reduced over a broad band of frequencies. For each bypass capacitor, a pair of conductive vias is formed. A first via is coupled to the LGA package Vcc plane and to the IC Vdd node, and a second via is coupled to the LGA package Vss plane and to the IC Vss node. These vias preferably are spaced-apart a distance &Dgr;X corresponding to the distance between first and second connections on the bypass capacitor although sub-mm offsets in a via at connections may be used to accommodate differing connection pitches. The bypass capacitor connections are coupled to the lower surfaces of the first and second vias, at the lower surface of the LGA package. When the package is inserted into a socket, the bypass capacitor extends into at least some of the otherwise unused recess in the socket. Multiple bypass capacitors are accommodated by forming additional spaced-apart vias that may be electrically parallel-coupled.

    Abstract translation: 在LGA封装或PGA封装的IC Vdd和IC Vss节点中的开关噪声通过在旁路通路中扩展电流来减少有效电流环路面积，从而减少存储在电流路径周围的磁场中的能量 。 通过最小化待旁路的IC节点与旁路电容器之间的连接路径的水平分量来实现该结果。 由于旁路电容器看到的有效电感Leff与磁能成比例，所以Leff在宽频带上减小。 对于每个旁路电容器，形成一对导电通孔。 第一通孔耦合到LGA封装Vcc平面和IC Vdd节点，并且第二通孔耦合到LGA封装Vss平面和IC Vss节点。 这些通孔优选地间隔开对应于旁路电容器上的第一和第二连接之间的距离的距离DELTA，尽管连接处的通孔中的mm-mm偏移可以用于适应不同的连接间距。 旁路电容器连接在LGA封装的下表面处连接到第一和第二通孔的下表面。 当封装插入插座时，旁路电容器延伸到插座中的其他未使用的凹部中的至少一些。 多个旁路电容器通过形成可以电并联耦合的附加间隔开的通孔来容纳。

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