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公开(公告)号：US20160064318A1
公开(公告)日：2016-03-03
申请号：US14840236
申请日：2015-08-31
Applicant: IBIDEN CO., LTD.
Inventor： Yasushi INAGAKI , Osamu Futonagane
IPC: H01L23/498 , H01L21/48 , H01P3/08 , H05K1/02
CPC classification number: H01L23/49822 , H01L21/4857 , H01L21/486 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311
Abstract: A package substrate includes an outermost interlayer, an outermost conductive layer including first pads positioned to mount at electronic component and second pads positioned to mount another electronic component, a first conductive layer including first circuits and formed such that the outermost interlayer is on the first conductive layer and that the first circuits are connecting the first and second pads, an inner interlayer formed such that the first conductive layer is on the inner interlayer, a second conductive layer formed such that the inner interlayer is on the second conductive layer, via conductors penetrating through the outermost interlayer and including first via conductors connecting the first conductive layer and the first pads and second via conductors connecting the first conductive layer and the second pads, and third via conductors penetrating through the inner interlayer and positioned such that the first and third via conductors form stacked via conductors.
Abstract translation: 封装衬底包括最外层中间层，最外层导电层包括定位成安装在电子部件上的第一焊盘和定位成安装另一电子部件的第二焊盘;第一导电层，包括第一电路，并且形成为使得最外层间处于第一导电 并且所述第一电路连接所述第一和第二焊盘，形成为使得所述第一导电层在所述内部中间层上的内部中间层，形成为使得所述内部中间层在所述第二导电层上的第二导电层， 通过最外层并且包括连接第一导电层和第一焊盘的第一通孔导体和连接第一导电层和第二焊盘的第二通孔导体，以及穿过内夹层的第三通孔导体，并且定位成使得第一和第三通孔 导体形成堆叠通孔导体。
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公开(公告)号：US10095330B2
公开(公告)日：2018-10-09
申请号：US15082407
申请日：2016-03-28
Applicant: IBIDEN CO., LTD.
Inventor： Toru Furuta , Osamu Futonagane
Abstract: A printed wiring board includes a first insulating layer, a first conductor circuit including fingerprint authentication circuitry and embedded in the first insulating layer such that the first circuit has exposed surface exposed from surface of the first insulating layer, a second insulating layer on which the first insulating layer is formed, a second conductor circuit including fingerprint authentication circuitry and embedded in the second insulating layer such that the second circuit has exposed surface exposed from surface of the second insulating layer and is interposed between the first and second insulating layers, and a solder resist layer formed on the surface of the first insulating layer and covering the first circuit. The first and second circuits are positioned such that the first and second circuits are opposing each other across the first insulating layer and that a finger for fingerprint authentication is placed on the solder resist layer.
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公开(公告)号：US09716059B2
公开(公告)日：2017-07-25
申请号：US14840236
申请日：2015-08-31
Applicant: IBIDEN CO., LTD.
Inventor： Yasushi Inagaki , Osamu Futonagane
IPC: H05K1/11 , H01L23/498 , H01L21/48 , H01L23/50
CPC classification number: H01L23/49822 , H01L21/4857 , H01L21/486 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311
Abstract: A package substrate includes an outermost interlayer, an outermost conductive layer including first pads positioned to mount at electronic component and second pads positioned to mount another electronic component, a first conductive layer including first circuits and formed such that the outermost interlayer is on the first conductive layer and that the first circuits are connecting the first and second pads, an inner interlayer formed such that the first conductive layer is on the inner interlayer, a second conductive layer formed such that the inner interlayer is on the second conductive layer, via conductors penetrating through the outermost interlayer and including first via conductors connecting the first conductive layer and the first pads and second via conductors connecting the first conductive layer and the second pads, and third via conductors penetrating through the inner interlayer and positioned such that the first and third via conductors form stacked via conductors.
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