公开(公告)号：US20130252379A1

公开(公告)日：2013-09-26

申请号：US13621242

申请日：2012-09-15

Applicant: IBM Corporation

Inventor： Wiren D Becker ,  Jinwoo Choi ,  Tingdong Zhou

IPC: H01L21/768

CPC classification number: H01L21/76838 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K3/4629 ,  H05K2201/09309 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below and adjacent to the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas The Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.

Abstract translation: 多层陶瓷封装包括：具有需要供电的识别芯片/器件区域的信号层; 以及设置在信号层正上方或下方并相邻的相对侧上的电压功率（Vdd）层和接地（Gnd）层，并提供使用混合网格方案配置的第一参考网格平面和第二参考网格平面。 混合网格方案包括：在识别的芯片/设备区域的正上方或下方的第一区域中的全密度网格; 在芯片/设备区域的边缘的上方或下方的第二区域中的半密度网格; 和所有其他区域中的较宽的网格间距Vdd迹线对齐以与其他区域的信号线平行并相邻。 在与信号线平行且相邻的网格区域内提供更宽的轨迹。