Method for Sequencing a Polynucleotide
    1.
    发明申请

    公开(公告)号:US20200216890A1

    公开(公告)日:2020-07-09

    申请号:US16723315

    申请日:2019-12-20

    Applicant: IMEC VZW

    Abstract: A method for sequencing a template polynucleotide, comprising the steps of: a) Providing a sensor comprising: an active region comprising a source region, a drain region, and a channel region, a dielectric region on the channel region, a polymerase coupled to the dielectric region, the polymerase having an active site, the polymerase being separated from the dielectric region by a gap, one or more sensitizing means, a fluidic gate region to which the polymerase is exposed, a template polynucleotide bound to a primer, the template polynucleotide being bound to the polymerase; b) Exposing the polymerase to one or more nucleotide polyphosphates; and c) Electrically monitoring changes in the channel region electrical properties.

    Assay with digital readout
    2.
    发明授权

    公开(公告)号:US11371959B2

    公开(公告)日:2022-06-28

    申请号:US16715541

    申请日:2019-12-16

    Applicant: IMEC VZW

    Abstract: A device and a method for performing an assay is provided. The assay device, which may be used for determining the concentration of an analyte in a sample, includes a plurality of microchambers and a Field-effect transistor (FET) arranged at the bottom of each of the plurality of microchambers. Capture probe molecules for the analyte can be arranged within the plurality of microchambers such that each microchamber contains at most one capture probe molecule. The FET can be arranged in said microchamber to give a readable output signal based on binding of the analyte, or competitor to the analyte, with the capture probe molecule.

    Complementary Logic Device Comprising Metal-to-Insulator Transition Material
    3.
    发明申请
    Complementary Logic Device Comprising Metal-to-Insulator Transition Material 审中-公开
    包括金属到绝缘体转换材料的互补逻辑器件

    公开(公告)号:US20130187680A1

    公开(公告)日:2013-07-25

    申请号:US13744625

    申请日:2013-01-18

    CPC classification number: H03K19/20

    Abstract: A complementary logic technology is disclosed whereby a logic gate comprises at least two metal-to-insulator transition (MIT) elements and at least two thermoelectric elements, each MIT element being thermally coupled to a corresponding thermoelectric element. In logic gates, each electric signal at an input terminal of a logic gate is first converted into two complementary thermal signals, and these thermal signals in turn determine the status of the output terminal of the logic gate, thereby generating an electrical output signal inverse to the electrical input signal or an output signal which is a Boolean operation on input signals. The parallel connection(s) of thermoelectric elements of the logic gate is used to create corresponding thermal signals for each electrical input signal. The MIT elements of the logic gate are then arranged to, in response to the associated thermal signals, execute a Boolean operation.

    Abstract translation: 公开了一种互补逻辑技术,由此逻辑门包括至少两个金属至绝缘体转变(MIT)元件和至少两个热电元件,每个MIT元件热耦合到相应的热电元件。 在逻辑门中,逻辑门的输入端的每个电信号首先转换成两个互补的热信号,这些热信号又决定了逻辑门的输出端的状态,从而产生与 电输入信号或对输入信号进行布尔运算的输出信号。 逻辑门的热电元件的并联连接用于为每个电输入信号产生相应的热信号。 然后逻辑门的MIT元件被布置为响应于相关联的热信号执行布尔运算。

    Method for Forming a Sensor
    4.
    发明申请

    公开(公告)号:US20210159321A1

    公开(公告)日:2021-05-27

    申请号:US17099339

    申请日:2020-11-16

    Abstract: A method for forming a sensor is provided. The method includes: providing an active region comprising a channel having: a length, and a periphery consisting of one or more surfaces having said length, said periphery comprising a first part and a second part, each part having said length, the first part representing from 10 to 75% of the area of the periphery and the second part representing from 25 to 90% of the area of the periphery; providing a first dielectric structure on the entire first part, the first dielectric structure having a maximal equivalent oxide thickness; and providing a second dielectric structure on the entire second part, the second dielectric structure having a minimal equivalent oxide thickness larger than the maximal equivalent oxide thickness of the first dielectric structure.

    MAGNETIC STRUCTURE FOR MAGNETIC DEVICE

    公开(公告)号:US20210210678A1

    公开(公告)日:2021-07-08

    申请号:US17121279

    申请日:2020-12-14

    Abstract: The present disclosure relates to magnetic devices. In particular, the disclosure relates to magnetic memory and logic devices that employ the voltage control of magnetic anisotropy (VCMA) effect for magnetization switching. The present disclosure provides a method for manufacturing a magnetic structure for such a magnetic device. The method comprising the following steps: providing a bottom electrode layer, forming a SrTiO3 (STO) stack on the bottom electrode layer by atomic layer deposition (ALD) of at least two different STO nanolaminates, forming a magnetic layer on the STO stack, and forming a perpendicular magnetic anisotropy (PMA) promoting layer on the magnetic layer, the PMA promoting layer being configured to promote PMA in the magnetic layer.

    Cyclic Capillary Electrophoresis Device

    公开(公告)号:US20210080427A1

    公开(公告)日:2021-03-18

    申请号:US17018368

    申请日:2020-09-11

    Abstract: A cyclic capillary electrophoresis device includes a capillary channel that forms a closed loop. The capillary channel comprises an inner half facing toward a space enclosed by the loop, where the inner half having an inner wall of first charge density, and an outer half facing away from the space enclosed by the loop, where the outer half having an inner wall surface of second charge density. A difference between the first and the second charge densities exists or can be turned on. The difference is configured to create a smaller average electroosmotic flow velocity in the inner half than in the outer half.

    Magnetic memory having multiple gates and method of operating same

    公开(公告)号:US10008251B2

    公开(公告)日:2018-06-26

    申请号:US15597056

    申请日:2017-05-16

    CPC classification number: G11C11/1675 G11C11/15 G11C11/161 H01L43/08

    Abstract: The disclosed technology generally relates to magnetic memory and more particularly to voltage-controlled magnetic memory, and to methods of using same. In one aspect, a magnetic memory comprises a first magnetic stack including a first gate dielectric layer formed between a first gate electrode and a first free ferromagnetic layer. The magnetic memory additionally comprises a second magnetic stack including a second gate dielectric layer formed between a second gate electrode and a second free ferromagnetic layer. The first free ferromagnetic layer and the second free ferromagnetic layer of the magnetic memory are magnetically coupled, contiguous and are positioned at an oblique angle relative to each other, and the first gate electrode and the second gate electrode are electrically isolated from each other.

    MAGNETIC MEMORY HAVING MULTIPLE GATES AND METHOD OF OPERATING SAME

    公开(公告)号:US20170301383A1

    公开(公告)日:2017-10-19

    申请号:US15597056

    申请日:2017-05-16

    CPC classification number: G11C11/1675 G11C11/15 G11C11/161 H01L43/08

    Abstract: The disclosed technology generally relates to magnetic memory and more particularly to voltage-controlled magnetic memory, and to methods of using same. In one aspect, a magnetic memory comprises a first magnetic stack including a first gate dielectric layer formed between a first gate electrode and a first free ferromagnetic layer. The magnetic memory additionally comprises a second magnetic stack including a second gate dielectric layer formed between a second gate electrode and a second free ferromagnetic layer. The first free ferromagnetic layer and the second free ferromagnetic layer of the magnetic memory are magnetically coupled, contiguous and are positioned at an oblique angle relative to each other, and the first gate electrode and the second gate electrode are electrically isolated from each other.

    BIO-FET-BASED PEPTIDE SEQUENCING METHOD AND DEVICE

    公开(公告)号:US20240218441A1

    公开(公告)日:2024-07-04

    申请号:US18397221

    申请日:2023-12-27

    Applicant: IMEC VZW

    CPC classification number: C12Q1/6869 C12Q1/6825

    Abstract: The present disclosure relates to single-peptide sequencing. A method for sequencing peptides is provided that includes attaching a base end of a peptide to a channel region surface of a biosensor field effect transistor (bio-FET) and obtaining a first measurement of a parameter of the bio-FET, the parameter depending on the bio-FET's threshold voltage. The method further includes providing first molecular probes into the electrolyte gate, each first molecular probe being linked to a respective charge tag, and obtaining a second measurement of the parameter. Then, the method includes determining whether a shift of the parameter occurred between the first and second measurements, which indicates that a first molecular probe attached to an amino acid at a free end of the peptide. If the shift of the parameter occurred, the method includes determining a type of the amino acid based on a type of the first molecular probe.

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