公开(公告)号：US20170077281A1

公开(公告)日：2017-03-16

申请号：US15122627

申请日：2014-06-13

Applicant: INTEL CORPORATION

Inventor： Kimin JUN ,  Sansaptak DASGUPTA ,  Alejandro X. LEVANDER ,  Patrick MORROW

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/04 ,  H01L29/20 ,  H01L29/66 ,  H01L21/78

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/76254 ,  H01L21/7806 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

Abstract translation: 一种包括在牺牲基板上的极性化合物半导体层上形成阻挡层的方法; 将牺牲衬底耦合到载体衬底以形成其中阻挡层设置在极性化合物半导体层和载体衬底之间的复合结构; 将牺牲衬底与复合结构分离以暴露极化合物半导体层; 以及形成至少一个电路装置。 一种在基板上包括阻挡层的装置; 阻挡层上的晶体管器件; 以及设置在所述阻挡层和所述晶体管器件之间的极性化合物半导体层，所述极性化合物半导体层包含二维电子气。

公开(公告)号：US20170229565A1

公开(公告)日：2017-08-10

申请号：US15329216

申请日：2014-09-09

Applicant: INTEL CORPORATION

Inventor： Kimin JUN ,  Sansaptak DASGUPTA ,  Alejandro X. LEVANDER ,  Patrick MORROW

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7781 ,  H01L21/76254 ,  H01L29/2003 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/66545

Abstract: A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.