公开(公告)号：US10331550B2

公开(公告)日：2019-06-25

申请号：US15282700

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： David Keppel ,  Charles J. Archer

IPC: G06F13/00 ,  G06F12/02 ,  G06F12/1009

Abstract: This disclosure describes, in one embodiment an apparatus. The apparatus includes a processor; a memory, an application, collector circuitry and aggregator circuitry. The memory is to store one or more tasks. The application is associated with the one or more tasks. The collector circuitry is to identify a local free address range in at least one address space. The aggregator circuitry is to provide address range data to a subgroup aggregator. The provided address range data includes at least one local free address range.

公开(公告)号：US20180217925A1

公开(公告)日：2018-08-02

申请号：US15282700

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： David Keppel ,  Charles J. Archer

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F12/0284 ,  G06F12/0292 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/656 ,  G06F2212/657

Abstract: This disclosure describes, in one embodiment an apparatus. The apparatus includes a processor; a memory, an application, collector circuitry and aggregator circuitry. The memory is to store one or more tasks. The application is associated with the one or more tasks. The collector circuitry is to identify a local free address range in at least one address space. The aggregator circuitry is to provide address range data to a subgroup aggregator. The provided address range data includes at least one local free address range.