公开(公告)号：US20250110812A1

公开(公告)日：2025-04-03

申请号：US18979399

申请日：2024-12-12

Applicant: Intel Corporation

Inventor： Yingqi LU ,  Smita KUMAR ,  Tracy Garrett DRYSDALE ,  Ranjit MENON ,  Toby OPFERMAN ,  Deepak GANDIGA SHIVAKUMAR ,  Stephen DOYLE ,  Corey D. GOUGH

IPC: G06F9/54

Abstract: Examples described herein relate to a processor to execute the instructions to cause: issue a first call to an application program interface (API) to an accelerator to cause the accelerator to compress data. In some examples, the API is to indicate whether the data is to be preserved in a buffer. In some examples, the API is to indicate a first offset. In some examples, the accelerator is to store the data starting at an address that is the first offset from a beginning address of the buffer allocated in a memory device. In some examples, the accelerator is to store the compressed data starting at a second offset from the beginning address of the buffer while the data is also stored in the buffer.

公开(公告)号：US20240273028A1

公开(公告)日：2024-08-15

申请号：US18600496

申请日：2024-03-08

Applicant: Intel Corporation

Inventor： Corey D. GOUGH ,  Yuval BUSTAN ,  Arvind RAMAN ,  Mariusz ORIOL ,  Nilanjan PALIT ,  Philip ABRAHAM ,  Priyanka GANESH ,  Daniel G. CARTAGENA ,  Mateusz DUCHALSKI

IPC: G06F12/0842 ,  G06F1/3206 ,  G06F1/3293 ,  G06F12/084

CPC classification number: G06F12/0842 ,  G06F1/3206 ,  G06F1/3293 ,  G06F12/084

Abstract: Examples described herein relate to at least one multi-core processor and a circuitry can determine and output energy usage of a process regardless of a core of the at least one multi-core processor that executes the process. The circuitry can determine the energy usage of the process based on cache operations and processor microoperations associated with the process. The energy usage of the process can be based on dynamic capacitance (Cdyn) levels and one or more of: temperature of the at least one multi-core processor, input voltage temperature to the at least one multi-core processor, and/or frequency of the at least one multi-core processor.

公开(公告)号：US20190384348A1

公开(公告)日：2019-12-19

申请号：US16480830

申请日：2017-02-24

Applicant: INTEL CORPORATION

Inventor： Vasudevan SRINIVASAN ,  Krishnakanth V. SISTLA ,  Corey D. GOUGH ,  Ian M. STEINER ,  Nikhil GUPTA ,  Vivek GARG ,  Ankush VARMA ,  Sujal A. VORA ,  David P. LERNER ,  Joseph M. SULLIVAN ,  Nagasubramanian GURUMOORTHY ,  William J. BOWHILL ,  Venkatesh RAMAMURTHY ,  Chris MACNAMARA ,  John J. BROWNE ,  Ripan DAS

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.