公开(公告)号：US20210103481A1

公开(公告)日：2021-04-08

申请号：US16969728

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Francesc Guim BERNAT ,  Karthik KUMAR ,  Susanne M. BALLE ,  Ignacio ASTILLEROS DIEZ ,  Timothy VERRALL ,  Ned M. SMITH

IPC: G06F9/50 ,  G06F9/48

Abstract: Technologies for providing efficient migration of services include a server device. The server device includes compute engine circuitry to execute a set of services on behalf of a terminal device and migration accelerator circuitry. The migration accelerator circuitry is to determine whether execution of the services is to be migrated from an edge station in which the present server device is located to a second edge station in which a second server device is located, determine a prioritization of the services executed by the server device, and send, in response to a determination that the services are to be migrated and as a function of the determined prioritization, data utilized by each service to the second server device of the second edge station to migrate the services. Other embodiments are also described and claimed.

公开(公告)号：US20180165213A1

公开(公告)日：2018-06-14

申请号：US15719491

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Francesc Guim BERNAT ,  Kshitij A. DOSHI ,  Robert G. BLANKENSHIP

IPC: G06F12/0884

Abstract: A request is received from a first node over a communication fabric, the request to acquire an access right of a cache line for accessing data stored in a memory location of a memory, the first node being one of a plurality of nodes sharing the memory. In response to the request, a second node is determined based on the cache line that has cached a copy of the data of the cache line in its local memory. A first message is transmitted to the second node over the communication fabric requesting the second node to invalidate the cache line. In response to a response received from the second node indicating that the cache line has been invalidated, a second message is transmitted to the first node over the communication fabric to grant the access right of the cache line to the first node.