公开(公告)号：US12020031B2

公开(公告)日：2024-06-25

申请号：US17334901

申请日：2021-05-31

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Jason W. Brandt ,  Gilbert Neiger ,  Asit K. Mallick ,  Rajesh M. Sankaran ,  Raghunandan Makaram ,  Benjamin C. Chaffin ,  James B. Crossland ,  H. Peter Anvin

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F13/40

CPC classification number: G06F9/3009 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/485 ,  G06F13/4068

Abstract: A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

公开(公告)号：US20220413859A1

公开(公告)日：2022-12-29

申请号：US17358082

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kameswar Subramaniam ,  Jason W. Brandt ,  H. Peter Anvin ,  Christopher M. Russell ,  Gilbert Neiger

IPC: G06F9/30 ,  G06F9/455 ,  G06F9/48

Abstract: In one embodiment, a processor includes: a front end circuit to fetch and decode a read list instruction, the read list instruction to cause storage to a memory of a software-provided list of processor state information; and an execution circuit coupled to the front end circuit. The execution circuit, in response to the decoded read list instruction, is to read the processor state information stored in the processor and store each datum of the processor state information into an entry of a data table in the memory. Other embodiments are described and claimed.

公开(公告)号：US20160378692A1

公开(公告)日：2016-12-29

申请号：US15232624

申请日：2016-08-09

Applicant: Intel Corporation

Inventor： H. Peter Anvin ,  Martin G. Dixon

IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/0817 ,  G06F12/1045

CPC classification number: G06F12/1475 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/30185 ,  G06F9/3877 ,  G06F12/0817 ,  G06F12/1009 ,  G06F12/1045 ,  G06F12/14 ,  G06F12/1466 ,  G06F2212/1052 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2212/68

Abstract: Instructions and logic provide memory key protection functionality. Embodiments include a processor having a register to store a memory protection field. A decoder decodes an instruction having an addressing form field for a memory operand to specify one or more memory addresses, and a memory protection key. One or more execution units, responsive to the memory protection field having a first value and to the addressing form field of the decoded instruction having a second value, enforce memory protection according to said first value of the memory protection field, using the specified memory protection key, for accessing the one or more memory addresses, and fault if a portion of the memory protection key specified by the decoded instruction does not match a stored key value associated with the one or more memory addresses.

Abstract translation: 说明和逻辑提供内存密钥保护功能。 实施例包括具有用于存储存储器保护域的寄存器的处理器。 解码器对具有用于存储器操作数的寻址形式字段的指令进行解码以指定一个或多个存储器地址以及存储器保护密钥。 一个或多个执行单元，响应于具有第一值的存储器保护域和具有第二值的解码指令的寻址形式字段，使用指定的存储器保护根据存储器保护字段的所述第一值强制存储器保护 键，用于访问所述一个或多个存储器地址，以及如果由所解码的指令指定的所述存储器保护密钥的一部分与所述一个或多个存储器地址相关联的存储的密钥值不匹配，则发生故障。

公开(公告)号：US11023233B2

公开(公告)日：2021-06-01

申请号：US15019112

申请日：2016-02-09

Applicant: INTEL CORPORATION

Inventor： Michael Mishaeli ,  Jason W. Brandt ,  Gilbert Neiger ,  Asit K. Mallick ,  Rajesh M. Sankaran ,  Raghunandan Makaram ,  Benjamin C. Chaffin ,  James B. Crossland ,  H. Peter Anvin

IPC: G06F9/30 ,  G06F13/40 ,  G06F9/48 ,  G06F9/38

Abstract: A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

公开(公告)号：US20210357214A1

公开(公告)日：2021-11-18

申请号：US17334901

申请日：2021-05-31

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Jason W. Brandt ,  Gilbert Neiger ,  Asit K. Mallick ,  Rajesh M. Sankaran ,  Raghunandan Makaram ,  Benjamin C. Chaffin ,  James B. Crossland ,  H. Peter Anvin

IPC: G06F9/30 ,  G06F13/40 ,  G06F9/48 ,  G06F9/38

Abstract: A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

公开(公告)号：US10999284B2

公开(公告)日：2021-05-04

申请号：US17084406

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Gilbert Neiger ,  H. Peter Anvin ,  Asit K. Mallick ,  Adriaan Van De Ven ,  Scott D. Rodgers

IPC: G06F21/00 ,  H04L29/06 ,  G06F21/74

Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.

公开(公告)号：US10135825B2

公开(公告)日：2018-11-20

申请号：US14582829

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Gilbert Neiger ,  H. Peter Anvin ,  Asit K. Mallick ,  Adriaan Van De Ven ,  Scott D. Rodgers

IPC: G06F21/00 ,  H04L29/06 ,  G06F21/74

Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.

公开(公告)号：US09740644B2

公开(公告)日：2017-08-22

申请号：US14498884

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： H. Peter Anvin ,  Gilbert Neiger

IPC: G06F9/30 ,  G06F13/24 ,  G11C7/10

CPC classification number: G06F13/24 ,  G06F9/327 ,  G06F9/4812 ,  G11C7/1072

Abstract: A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20170228233A1

公开(公告)日：2017-08-10

申请号：US15019112

申请日：2016-02-09

Applicant: INTEL CORPORATION

Inventor： Michael Mishaeli ,  Jason W. Brandt ,  Gilbert Neiger ,  Asit K. Mallick ,  Rajesh M. Sankaran ,  Raghunandan Makaram ,  Benjamin C. Chaffin ,  James B. Crossland ,  H. Peter Anvin

IPC: G06F9/30 ,  G06F13/40

CPC classification number: G06F9/3009 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/52 ,  G06F13/4068

Abstract: A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

公开(公告)号：US09411600B2

公开(公告)日：2016-08-09

申请号：US14099954

申请日：2013-12-08

Applicant: Intel Corporation

Inventor： H. Peter Anvin ,  Martin G. Dixon

IPC: G06F11/10 ,  G06F9/38 ,  G06F12/14 ,  G06F9/30

CPC classification number: G06F12/1475 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/30185 ,  G06F9/3877 ,  G06F12/0817 ,  G06F12/1009 ,  G06F12/1045 ,  G06F12/14 ,  G06F12/1466 ,  G06F2212/1052 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2212/68

Abstract: Instructions and logic provide memory key protection functionality. Embodiments include a processor having a register to store a memory protection field. A decoder decodes an instruction having an addressing form field for a memory operand to specify one or more memory addresses, and a memory protection key. One or more execution units, responsive to the memory protection field having a first value and to the addressing form field of the decoded instruction having a second value, enforce memory protection according to said first value of the memory protection field, using the specified memory protection key, for accessing the one or more memory addresses, and fault if a portion of the memory protection key specified by the decoded instruction does not match a stored key value associated with the one or more memory addresses.

Abstract translation: 说明和逻辑提供内存密钥保护功能。 实施例包括具有用于存储存储器保护域的寄存器的处理器。 解码器对具有用于存储器操作数的寻址形式字段的指令进行解码以指定一个或多个存储器地址以及存储器保护密钥。 一个或多个执行单元，响应于具有第一值的存储器保护域和具有第二值的解码指令的寻址形式字段，使用指定的存储器保护根据存储器保护字段的所述第一值强制存储器保护 键，用于访问所述一个或多个存储器地址，以及如果由所解码的指令指定的所述存储器保护密钥的一部分与所述一个或多个存储器地址相关联的存储的密钥值不匹配，则发生故障。