公开(公告)号：US20180350932A1

公开(公告)日：2018-12-06

申请号：US15778304

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： EN-SHAO LIU ,  JOODONG PARK ,  CHEN-GUAN LEE ,  JUI-YEN LIN ,  CHIA-HONG Jan

IPC: H01L29/423 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/764

CPC classification number: H01L29/42376 ,  B82Y10/00 ,  H01L21/32133 ,  H01L21/764 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ⊥-shape, L-shape, or J-shape, for example.

公开(公告)号：US20160056293A1

公开(公告)日：2016-02-25

申请号：US14780218

申请日：2013-06-26

Applicant: INTEL CORPORATION

Inventor： JENG-YA D. YEH ,  CHIA-HONG JAN ,  WALID M. HAFEZ ,  JOODONG PARK

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L29/42368 ,  H01L29/66795 ,  H01L29/785

Abstract: Non-planar semiconductor devices having self-aligned fins with top blocking layers and methods of fabricating non-planar semiconductor devices having self-aligned fins with top blocking layers are described. For example, a semiconductor structure includes a semiconductor fin disposed above a semiconductor substrate and having a top surface. An isolation layer is disposed on either side of the semiconductor fin, and recessed below the top surface of the semiconductor fin to provide a protruding portion of the semiconductor fin. The protruding portion has sidewalls and the top surface. A gate blocking layer has a first portion disposed on at least a portion of the top surface of the semiconductor fin, and has a second portion disposed on at least a portion of the sidewalls of the semiconductor fin. The first portion of the gate blocking layer is continuous with, but thicker than, the second portion of the gate blocking layer. A gate stack is disposed on the first and second portions of the gate blocking layer.

Abstract translation: 描述了具有顶部阻挡层的自对准翅片的非平面半导体器件以及制造具有顶部阻挡层的具有自对准翅片的非平面半导体器件的方法。 例如，半导体结构包括设置在半导体衬底之上并具有顶表面的半导体鳍片。 隔离层设置在半导体鳍片的任一侧，并且在半导体鳍片的顶表面下方凹进，以提供半导体鳍片的突出部分。 突出部具有侧壁和顶面。 栅极阻挡层具有设置在半导体鳍片的顶表面的至少一部分上的第一部分，并且具有设置在半导体鳍片的至少一部分侧壁上的第二部分。 栅极阻挡层的第一部分与栅极阻挡层的第二部分连续但是比第二部分更厚。 栅极堆叠设置在栅极阻挡层的第一和第二部分上。

公开(公告)号：US20200006509A1

公开(公告)日：2020-01-02

申请号：US16569879

申请日：2019-09-13

Applicant: INTEL CORPORATION

Inventor： EN-SHAO LIU ,  JOODONG PARK ,  CHEN-GUAN LEE ,  JUI-YEN LIN ,  CHIA-HONG Jan

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/764

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US20160197082A1

公开(公告)日：2016-07-07

申请号：US14912890

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： JOODONG PARK ,  GOPINATH BHIMARASETTI ,  RAHUL RAMASWAMY ,  CHIA-HONG JAN ,  WALID M. HAFEZ ,  JENG-YA D. YEH ,  CURTIS TSAI

IPC: H01L27/108

CPC classification number: H01L27/10826 ,  H01L27/10808 ,  H01L27/10879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854

Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.

Abstract translation: 描述了用于嵌入式动态随机存取存储器（eDRAM）的低泄漏非平面存取晶体管和用于制造用于eDRAM的低泄漏非平面存取晶体管的方法。 例如，半导体器件包括设置在衬底上方并且包括设置在两个宽鳍片区域之间的窄鳍区域的半导体鳍片。 栅电极堆叠被配置为与半导体鳍片的窄鳍区域共形，栅电极堆叠包括设置在栅介质层上的栅电极。 栅介质层包括下层和上层，下层由半导体鳍片的氧化物构成。 包括一对源极/漏极区域，每个源极/漏极区域布置在相应的一个宽鳍片区域中。

公开(公告)号：US20180374927A1

公开(公告)日：2018-12-27

申请号：US15778306

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： EN-SHAO LIU ,  JOODONG PARK ,  CHEN-GUAN LEE ,  CHIA-HONG Jan

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/764 ,  H01L21/28

CPC classification number: H01L29/4991 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a “T” shape or various derivatives of that shape such as -shape or -shape, for example.

公开(公告)号：US20160211369A1

公开(公告)日：2016-07-21

申请号：US14913326

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： CHIA-HONG JAN ,  WALID M. HAFEZ ,  CURTIS TSAI ,  JENG-YA D. YEH ,  JOODONG PARK

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L27/12 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.

Abstract translation: 描述了用于片上系统（SoC）应用的垂直非平面半导体器件和制造垂直非平面半导体器件的方法。 例如，半导体器件包括设置在衬底上方的半导体鳍片，半导体鳍片具有凹部和最上部。 源极区域设置在半导体鳍片的凹部中。 漏极区域设置在半导体鳍片的最上部。 栅电极设置在半导体鳍片的最上部分之间，在源区和漏区之间。

公开(公告)号：US20190027604A1

公开(公告)日：2019-01-24

申请号：US16081215

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： CHEN-GUAN LEE ,  WALID M. HAFEZ ,  JOODONG PARK ,  CHIA-HONG JAN ,  HSU-YU CHANG

IPC: H01L29/78 ,  H01L29/66

Abstract: Techniques are disclosed for forming a transistor with enhanced thermal performance. The enhanced thermal performance can be derived from the inclusion of thermal boost material adjacent to the transistor, where the material can be selected based on the transistor type being formed. In the case of PMOS devices, the adjacent thermal boost material may have a high positive linear coefficient of thermal expansion (CTE) (e.g., greater than 5 ppm/° C. at around 20° C.) and thus expand as operating temperatures increase, thereby inducing compressive strain on the channel region of an adjacent transistor and increasing carrier (e.g., hole) mobility. In the case of NMOS devices, the adjacent thermal boost material may have a negative linear CTE (e.g., less than 0 ppm/° C. at around 20° C.) and thus contract as operating temperatures increase, thereby inducing tensile strain on the channel region of an adjacent transistor and increasing carrier (e.g., electron) mobility.

公开(公告)号：US20170069725A1

公开(公告)日：2017-03-09

申请号：US15122796

申请日：2014-06-26

Applicant: Intel Corporation

Inventor： GOPINATH BHIMARASETTI ,  WALID M. HAFEZ ,  JOODONG PARK ,  WEIMIN HAN ,  RAYMOND E. COTNER ,  CHIA-HONG JAN

IPC: H01L29/36 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/36 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7853

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Abstract translation: 描述了具有掺杂子鳍区域的ω鳍片的非平面半导体器件以及制造具有掺杂子鳍片区域的具有Ω形翅片的非平面半导体器件的方法。 例如，半导体器件包括设置在半导体衬底上方的多个半导体鳍片，每个半导体鳍片具有在突出部分下方的副鳍片部分，子鳍片部分比突出部分窄。 固态掺杂剂源层设置在半导体衬底之上，与子鳍区域共形而不是多个半导体鳍片中的每一个的突出部分。 隔离层设置在固态掺杂剂源层上方和多个半导体鳍片的子鳍片区域之间。 栅极叠层设置在隔离层上方并与多个半导体鳍片中的每一个的突起部分保形。

公开(公告)号：US20160035735A1

公开(公告)日：2016-02-04

申请号：US14880814

申请日：2015-10-12

Applicant: INTEL CORPORATION

Inventor： WALID M. HAFEZ ,  CHIA-HONG JAN ,  CURTIS TSAI ,  JOODONG PARK ,  JENG-YA D. YEH

IPC: H01L27/112

CPC classification number: H01L27/11206 ,  H01L21/823821 ,  H01L23/5252 ,  H01L27/0924 ,  H01L29/7853 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.

Abstract translation: 本文公开了用于提供非易失性反熔丝存储元件和其它反熔丝链路的技术。 在一些实施例中，反熔丝存储器元件被配置为非平面拓扑，例如FinFET拓扑。 在一些这样的实施例中，可以通过产生适合用于较低电压非易失性反熔丝存储器元件的增强发射位点来操纵翅片拓扑并用于有效地促进较低击穿电压晶体管。 在一个示例实施例中，提供了一种半导体反熔丝装置，其包括具有锥形部分的翅片的非平面扩散区域，在包括锥形部分的鳍片上的介电隔离层和介电隔离层上的栅极材料。 翅片的锥形部分可以例如通过氧化，蚀刻和/或烧蚀形成，并且在一些情况下包括基底区域和变薄区域，并且变薄区域比基底区域薄至少50％ 。