中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.018 seconds)

    Packet processing on graphics processing units using continuous threads
    1.
    发明授权
    Packet processing on graphics processing units using continuous threads 有权

    公开(公告)号：US09830676B2

    公开(公告)日：2017-11-28

    申请号：US14810684

    申请日：2015-07-28

    Applicant: Intel Corporation

    Inventor： Janet Tseng ,  Felix J. Degrood ,  Alexander W. Min ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai

    IPC: G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06T1/60

    Abstract: In accordance with some embodiments, a continuous thread is operated on the graphics processing unit. A continuous thread is launched one time from the central processing unit and then it runs continuously until an application on the central processing unit decides to terminate the thread. For example, the application may decide to terminate the thread in one of a variety of situations which may be programmed in advance. For example, upon error detection, a desire to change the way that the thread on the graphics processing unit operates, or in power off, the thread may terminate. But unless actively terminated by the central processing unit, the continuous thread generally runs uninterrupted.

    [ICE] ARCHITECTURE AND MECHANISMS TO ACCELERATE TUPLE-SPACE SEARCH WITH INTERGRATED GPU
    3.
    发明申请
    [ICE] ARCHITECTURE AND MECHANISMS TO ACCELERATE TUPLE-SPACE SEARCH WITH INTERGRATED GPU 审中-公开

    公开(公告)号：US20190042304A1

    公开(公告)日：2019-02-07

    申请号：US15829938

    申请日：2017-12-03

    Applicant: Intel Corporation

    Inventor： Ren Wang ,  Janet Tseng ,  Jr-Shian Tsai ,  Tsung-Yuan Tai

    IPC: G06F9/48 ,  H04L12/851

    Abstract: Methods, apparatus, systems, and software for architectures and mechanisms to accelerate tuple-space search with integrated GPUs (Graphic Processor Units). One of the architectures employs GPU-side lookup table sorting, under which local and global hit count histograms are maintained for work groups, and sub-tables containing rules for tuple matching are re-sorted based on the relative hit rates of the different sub-tables. Under a second architecture, two levels of parallelism are implemented: packet-level parallelism and lookup table-parallelism. Under a third architecture, dynamic two-level parallel processing with pre-screen is implemented. Adaptive decision making mechanisms are also disclosed to select which architecture is optimal in view of multiple considerations, including application preferences, offered throughput, and available GPU resources. The architectures leverage utilization of both processor cores and GPU processing elements to accelerate tuple-space searches, including searches using wildcard masks.

    Techniques for routing packets between virtual machines
    5.
    发明授权
    Techniques for routing packets between virtual machines 有权

    公开(公告)号：US10567510B2

    公开(公告)日：2020-02-18

    申请号：US15722698

    申请日：2017-10-02

    Applicant: INTEL CORPORATION

    Inventor： Mesut A. Ergin ,  Jr-Shian Tsai ,  Janet Tseng ,  Ren Wang ,  Jun Nakajima ,  Tsung-Yuan Tai

    IPC: H04L12/50 ,  H04L29/08 ,  H04L12/725 ,  H04L12/721 ,  H04L12/713 ,  H04L12/835 ,  H04L12/26

    Abstract: Various embodiments are generally directed to techniques for improving the efficiency of exchanging packets between pairs of VMs within a communications server. An apparatus may include a processor component; a network interface to couple the processor component to a network; a virtual switch to analyze contents of at least one packet of a set of packets to be exchanged between endpoint devices through the network and the communications server, and to route the set of packets through one or more virtual servers of multiple virtual servers based on the contents; and a transfer component of a first virtual server of the multiple virtual servers to determine whether to route the set of packets to the virtual switch or to transfer the set of packets to a second virtual server of the multiple virtual servers in a manner that bypasses the virtual switch based on a routing rule.

    Technologies for offloading network packet processing to a GPU
    6.
    发明授权
    Technologies for offloading network packet processing to a GPU 有权

    公开(公告)号：US10445850B2

    公开(公告)日：2019-10-15

    申请号：US14836142

    申请日：2015-08-26

    Applicant: Intel Corporation

    Inventor： Alexander W. Min ,  Shinae Woo ,  Jr-Shian Tsai ,  Janet Tseng ,  Tsung-Yuan C. Tai

    IPC: G06T1/20 ,  H04L12/26 ,  H04L12/911 ,  H04L12/931 ,  H04L29/08 ,  H04L12/933

    Abstract: Technologies for offloading an application for processing a network packet to a graphics processing unit (GPU) of a network device. The network device is configured to determine resource criteria of the application and available resources of the GPU. The network device is further configured to determine whether the available GPU resources are sufficient to process the application based on the resource criteria of the application and the available GPU resources. Additionally, the network device is configured to determine one or more estimated GPU performance metrics based on the resource criteria of the application and the available GPU resources to determine whether to offload the application to the GPU. Other embodiments are described and claimed.

    Packet Processing on Graphics Processing Units Using Continuous Threads
    7.
    发明申请
    Packet Processing on Graphics Processing Units Using Continuous Threads 有权
    使用连续线程的图形处理单元的数据包处理

    公开(公告)号：US20170032486A1

    公开(公告)日：2017-02-02

    申请号：US14810684

    申请日：2015-07-28

    Applicant: Intel Corporation

    Inventor： Janet Tseng ,  Felix J. Degrood ,  Alexander W. Min ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai

    IPC: G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06T1/60

    Abstract: In accordance with some embodiments, a continuous thread is operated on the graphics processing unit. A continuous thread is launched one time from the central processing unit and then it runs continuously until an application on the central processing unit decides to terminate the thread. For example, the application may decide to terminate the thread in one of a variety of situations which may be programmed in advance. For example, upon error detection, a desire to change the way that the thread on the graphics processing unit operates, or in power off, the thread may terminate. But unless actively terminated by the central processing unit, the continuous thread generally runs uninterrupted.

    Abstract translation: 根据一些实施例，在图形处理单元上操作连续的线程。 连续线程从中央处理单元一次启动，然后连续运行，直到中央处理单元上的应用程序决定终止线程。 例如，应用程序可以决定在预先编程的各种情况之一中终止线程。 例如，在错误检测时，希望改变线程在图形处理单元上运行或断电的方式可能终止。 但除非中央处理单元主动终止，否则连续线程一般不间断运行。

    Technologies for classifying network flows using adaptive virtual routing
    9.
    发明申请
    Technologies for classifying network flows using adaptive virtual routing 审中-公开

    公开(公告)号：US20190044869A1

    公开(公告)日：2019-02-07

    申请号：US15999133

    申请日：2018-08-17

    Applicant: Intel Corporation

    Inventor： Yipeng Wang ,  Ren Wang ,  Janet Tseng ,  Jr-Shian Tsai ,  Tsung-Yuan Tai

    IPC: H04L12/851 ,  H04L12/931 ,  H04L12/713 ,  H04L12/26 ,  H04L29/08 ,  G06F11/34

    Abstract: Technologies for classifying network flows using adaptive virtual routing include a network appliance with one or more processors. The network appliance is configured to identify a set of candidate classification algorithms from a plurality of classification algorithm designs to perform a flow classification operation and deploy each of the candidate classification algorithms to a processor. Additionally the network appliance is configured to monitor a performance level of each of the deployed candidate classification algorithms and identify a candidate classification algorithm of the deployed candidate classification algorithms with the highest performance level. The network appliance is further configured to deploy the identified candidate classification algorithm with the highest performance level on each of the one or more processors that are configured to perform the flow classification operation. Other embodiments are described herein.

Patent Agency Ranking