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公开(公告)号:US20210312586A1
公开(公告)日:2021-10-07
申请号:US17180235
申请日:2021-02-19
Applicant: Intel Corporation
Inventor: Joydeep Ray , Ankur N. Shah , Abhishek R. Appu , Deepak S. Vembar , ElMoustapha Ould-Ahmed-Vall , Atsuo Kuwahara , Travis T. Schluessler , Linda L. Hurd , Josh B. Mastronarde , Vasanth Ranganathan
Abstract: An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.
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公开(公告)号:US10963986B2
公开(公告)日:2021-03-30
申请号:US16727073
申请日:2019-12-26
Applicant: INTEL CORPORATION
Inventor: Balaji Vembu , Josh B. Mastronarde , Altug Koker , Nikos Kaburlasos , Abhishek R. Appu , Joydeep Ray
Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive one or more frames for a workload, determine one or more compute resource parameters for the workload, and store the one or more compute resource parameters for the workload in a memory in association with workload context data for the workload. Other embodiments are also disclosed and claimed.
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公开(公告)号:US10929947B2
公开(公告)日:2021-02-23
申请号:US16572161
申请日:2019-09-16
Applicant: Intel Corporation
Inventor: Joydeep Ray , Ankur N. Shah , Abhishek R. Appu , Deepak S. Vembar , ElMoustapha Ould-Ahmed-Vall , Atsuo Kuwahara , Travis T. Schluessler , Linda L. Hurd , Josh B. Mastronarde , Vasanth Ranganathan
Abstract: An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.
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公开(公告)号:US20200210238A1
公开(公告)日:2020-07-02
申请号:US16726341
申请日:2019-12-24
Applicant: Intel Corporation
Inventor: Abhishek R Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20190095223A1
公开(公告)日:2019-03-28
申请号:US15716239
申请日:2017-09-26
Applicant: Intel Corporation
Inventor: William S. Dubel , Josh B. Mastronarde , Melaku Teshome
Abstract: Embodiments are generally directed to automatic waking of power domains for graphics configuration requests. An embodiment of an apparatus an interface to receive a graphics configuration request, wherein the graphics configuration request is directed to a target graphics register in a graphics domain; registers for storage of data, the registers including one or more configuration registers that are accessible for storage of the graphics configuration request; automatic power domain determination logic to determine a power domain for the target graphics register based on shared information accessed by the automatic power domain determination logic; and wake indication logic to determine whether the power domain for the target graphics register is in a reduced power state and, upon making a reduced power state determination, to generate a wake indication for the power domain.
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公开(公告)号:US20180308208A1
公开(公告)日:2018-10-25
申请号:US15819093
申请日:2017-11-21
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
CPC classification number: G06T1/20 , G06F8/41 , G06F9/45533 , G06F9/5061 , G06F9/5094 , G06F17/16 , G06F2009/45583 , G06T1/60
Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type
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公开(公告)号:US20180308205A1
公开(公告)日:2018-10-25
申请号:US15495956
申请日:2017-04-24
Applicant: Intel Corporation
Inventor: Balaji Vembu , Nikos Kaburlasos , Josh B. Mastronarde
CPC classification number: G06T1/20 , G06F1/3203 , G06F1/3231 , G06F1/3234 , G06F1/3265 , G06T1/60 , G09G2330/021 , G09G2340/0435 , G09G2354/00
Abstract: In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20180300847A1
公开(公告)日:2018-10-18
申请号:US15489015
申请日:2017-04-17
Applicant: Intel Corporation
Inventor: Balaji Vembu , Josh B. Mastronarde , Altug Koker , Nikos Kaburlasos , Abhishek R. Appu , Joydeep Ray
Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive one or more frames for a workload, determine one or more compute resource parameters for the workload, and store the one or more compute resource parameters for the workload in a memory in association with workload context data for the workload. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20180293697A1
公开(公告)日:2018-10-11
申请号:US15483623
申请日:2017-04-10
Applicant: Intel Corporation
Inventor: Joydeep Ray , Ankur N. Shah , Abhishek R. Appu , Deepak S. Vembar , ElMoustapha Ould-Ahmed-Vall , Atsuo Kuwahara , Travis T. Schluessler , Linda L. Hurd , Josh B. Mastronarde , Vasanth Ranganathan
CPC classification number: G06T1/20 , G06F9/30145 , G06F9/3851 , G06F9/3887 , G06T15/005
Abstract: An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.
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公开(公告)号:US12198221B2
公开(公告)日:2025-01-14
申请号:US18436494
申请日:2024-02-08
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.
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