公开(公告)号：US11500825B2

公开(公告)日：2022-11-15

申请号：US16105031

申请日：2018-08-20

Applicant: INTEL CORPORATION

Inventor： Ren Wang ,  Bruce Richardson ,  Tsung-Yuan Tai ,  Yipeng Wang ,  Pablo De Lara Guarch

IPC: G06F16/21 ,  G06F16/22

Abstract: Techniques and apparatus for dynamic data access mode processes are described. In one embodiment, for example, an apparatus may a processor, at least one memory coupled to the processor, the at least one memory comprising an indication of a database and instructions, the instructions, when executed by the processor, to cause the processor to determine a database utilization value for a database, perform a comparison of the database utilization value to at least one utilization threshold, and set an active data access mode to one of a low-utilization data access mode or a high-utilization data access mode based on the comparison. Other embodiments are described.

公开(公告)号：US20240113863A1

公开(公告)日：2024-04-04

申请号：US18129814

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Pablo De Lara Guarch ,  Tomasz Kantecki ,  Krystian Matusiewicz ,  Wajdi Feghali ,  Vinodh Gopal ,  James D. Guilford

IPC: H04L9/06 ,  H04L9/32 ,  H04W12/037

CPC classification number: H04L9/065 ,  H04L9/3215 ,  H04W12/037

Abstract: Methods and apparatus relating to an efficient implementation of ZUC authentication are described. In one embodiment, a processor computes a tag update, based at least in part on stored data, for an authentication operation. The tag update is computed by replacing a ‘for’ loop with a carry-less multiply operation. Other embodiments are also claimed and disclosed.

公开(公告)号：US20240048543A1

公开(公告)日：2024-02-08

申请号：US18237754

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Ping Yu ,  Tomasz Kantecki ,  Chao Dou ,  Pablo De Lara Guarch ,  Brian Will

IPC: H04L9/40 ,  H04L69/22

CPC classification number: H04L63/0485 ,  H04L69/22

Abstract: An apparatus includes an interface to memory, and a processor to execute one or more instructions. The instructions cause the processor to receive, via an application programming interface (API), a plurality of packets, respective packets of the plurality of packets comprising a respective header and a respective payload. Further, the instructions cause the processor to determine, by a QUIC protocol stack, to encrypt the plurality of packets in parallel. Further, the instructions cause the processor to encrypt the payloads of the plurality of packets in parallel. Further, the instructions cause the processor to encrypt the headers of the plurality of packets in parallel.