公开(公告)号：US20210200673A1

公开(公告)日：2021-07-01

申请号：US16728800

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： DEEPAK GUPTA ,  MINGWEI ZHANG ,  RAVI SAHITA ,  VEDVYAS SHANBHOGUE ,  MICHAEL LEMAY ,  DAVID M. DURHAM

IPC: G06F12/02 ,  G06F12/0895 ,  G06F9/30

Abstract: An apparatus and method for memory management using compartmentalization. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request using a first linear address; and address translation circuitry to perform a first walk operation through a set of one or more address translation tables to translate the first linear address to a first physical address, the address translation circuitry to concurrently perform a second walk operation through a set of one or more linear address metadata tables to identify metadata associated with the linear address, and to use one or more portions of the metadata to validate access by the at least one instruction to the first physical address.

公开(公告)号：US20190318082A1

公开(公告)日：2019-10-17

申请号：US16452916

申请日：2019-06-26

Applicant: INTEL CORPORATION

Inventor： ABHISHEK BASAK ,  RAVI SAHITA ,  VEDVYAS SHANBHOGUE

IPC: G06F21/52 ,  G06F12/06

Abstract: Various embodiments are generally directed to techniques for control flow protection with minimal performance overhead, such as by utilizing one or more micro-architectural optimizations to implement a shadow stack (SS) to verify a return address before returning from a function call, for instance. Some embodiments are particularly directed to a computing platform, such as an internet of things (IoT) platform, that overlaps or parallelizes one or more SS access operations with one or more data stack (DS) access operations.