公开(公告)号：US20230245974A1

公开(公告)日：2023-08-03

申请号：US18131829

申请日：2023-04-06

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark BOHR ,  Rajabali KODURI ,  Leonard NEIBERG ,  Altug KOKER ,  Swaminathan SIVAKUMAR

IPC: H01L23/538 ,  H01L21/78 ,  H01L21/66 ,  H01L23/528 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5386 ,  H01L21/78 ,  H01L22/20 ,  H01L23/528 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/94 ,  H01L25/18 ,  H01L23/481

Abstract: A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.

公开(公告)号：US20240245990A1

公开(公告)日：2024-07-25

申请号：US18433117

申请日：2024-02-05

Applicant: Intel Corporation

Inventor： Makarand DHARMAPURIKAR ,  Rajabali KODURI ,  Vijay BAHIRJI ,  Toby OPFERMAN ,  Scott G. CHRISTIAN ,  Rajeev PENMATSA ,  Selvakumar PANNEER

IPC: A63F13/355

CPC classification number: A63F13/355

Abstract: Described herein is a cloud-based gaming system in which graphics processing operations of a cloud-based game can be performed on a client device. Client-based graphics processing can be enabled in response to a determination that the client includes a graphics processor having a performance that exceeds a minimum threshold. When a game is remotely executed and streamed to a client, the client is configurable to provide network feedback that can be used to adjust execution and/or encoding for the game.

公开(公告)号：US20230317145A1

公开(公告)日：2023-10-05

申请号：US17711286

申请日：2022-04-01

Applicant: INTEL CORPORATION

Inventor： Abhishek Anil SHARMA ,  Pushkar RANADE ,  Wilfred GOMES ,  Rajabali KODURI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4094

Abstract: Methods and apparatus to implement an integrated circuit to operate based on data access characteristics. In one embodiment, the integrated circuit comprises a first array comprising a first plurality of memory cells, a second array comprising a second plurality of memory cells, both first and second arrays to store data of a processor, the second plurality of memory cells implementing a selector transistor of a memory cell within using a thin-film transistor (TFT), and a memory control circuit to write a first set of bits to the first array and a second set of bits to the second array upon determining the first set of bits is to be accessed more frequently than the second set of bits.

公开(公告)号：US20230315331A1

公开(公告)日：2023-10-05

申请号：US17711394

申请日：2022-04-01

Applicant: INTEL CORPORATION

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Rajabali KODURI

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: Methods and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM). In one embodiment, the integrated circuit comprises a static random-access memory (SRAM) device to store a first portion of data of a processor, a dynamic random-access memory (DRAM) device to store a second portion of the data of the processor, and a memory control circuit to read from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device.

公开(公告)号：US20200211970A1

公开(公告)日：2020-07-02

申请号：US16236228

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark BOHR ,  Rajabali KODURI ,  Leonard NEIBERG ,  Altug KOKER ,  Swaminathan SIVAKUMAR

IPC: H01L23/538 ,  H01L23/528 ,  H01L25/18 ,  H01L23/00 ,  H01L21/66 ,  H01L21/78

Abstract: A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.