公开(公告)号：US11301167B2

公开(公告)日：2022-04-12

申请号：US16414265

申请日：2019-05-16

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram

IPC: G06F3/06 ,  H03M13/29 ,  H03M13/00 ,  G06F3/00 ,  G11C7/10 ,  G06F11/10 ,  G06N3/08

Abstract: Technologies for providing multiple tier memory media management include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory compute operation. Additionally, the media access circuitry is to read, in response to the request, data from a memory media region of the memory media, write the read data into a compute media region of the memory, perform, on the data in the compute media region, the in-memory compute operation, write, to the memory media region, resultant data indicative of a result of performance of the in-memory compute operation.

公开(公告)号：US11126438B2

公开(公告)日：2021-09-21

申请号：US16452955

申请日：2019-06-26

Applicant: Intel Corporation

Inventor： Srikanth Srinivasan ,  Thomas Mullins ,  Ammon Christiansen ,  James Hadley ,  Robert S. Chappell ,  Sean Mirkes

IPC: G06F9/22 ,  G06F9/38 ,  G06F9/48

Abstract: In one embodiment, a reservation station of a processor includes: a plurality of first lanes having a plurality of entries to store information for instructions having in-order dependencies; a variable latency tracking table including a second plurality of entries to store information for instructions having a variable latency; and a scheduler circuit to access a head entry of the plurality of first lanes to schedule, for execution on at least one execution unit, at least one instruction from the head entry of at least one of the plurality of first lanes. Other embodiments are described and claimed.

公开(公告)号：US20190310911A1

公开(公告)日：2019-10-10

申请号：US16451545

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Wei Wu ,  Chetan Chauhan ,  Srikanth Srinivasan ,  Shigeki Tomishima

IPC: G06F11/10 ,  G11C29/52

Abstract: Technologies for provisioning error-corrected data for use in in-memory compute operations include a memory that includes a memory media having multiple memory partitions and media access circuitry coupled to the memory media. The media access circuitry is to receive a request to perform an in-memory compute operation on data from the memory media. The request specifies a memory partition of the memory media in which the data is located. The media access circuitry reads the data from the memory partition. The media access circuitry performs error correction on the read data to produce error-corrected read data and stores the error-corrected read data in a temporary buffer for access by one or more in-memory compute operations, in addition to the requested in-memory compute operation.

公开(公告)号：US20190227750A1

公开(公告)日：2019-07-25

申请号：US16370007

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Srikanth Srinivasan ,  Richard Coulson ,  Rajesh Sundaram ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Sriram Vangal ,  Wei Wu ,  Chetan Chauhan

IPC: G06F3/06

Abstract: Technologies for performing tensor operations in memory include a memory comprising media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is to access matrix data from the memory media, perform a tensor operation on the matrix data, and write, to the memory media, resultant data indicative of a result of the tensor operation.

公开(公告)号：US11620358B2

公开(公告)日：2023-04-04

申请号：US16411730

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Rajesh Sundaram ,  Richard Coulson ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F17/16 ,  G06F9/30

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

公开(公告)号：US20200104126A1

公开(公告)日：2020-04-02

申请号：US16147696

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Jonathan Pearce ,  David Sheffield ,  Srikanth Srinivasan ,  Jeffrey Cook ,  Deborah Marr ,  Abhijit Davare ,  Asit Mishra ,  Steven Burns ,  Desmond Kirkpatrick ,  Andrey Ayupov ,  Anton Alexandrovich Sorokin ,  Eriko Nurvitadhi

IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16 ,  G06F12/0831 ,  G06F12/084 ,  G06F7/57

Abstract: An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule a plurality of matrix operations responsive to a tensor matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, each lane comprising: first, second, and third tile registers to store blocks of a first matrix (A), second matrix (B), and third matrix (C), respectively; at least one tensor arithmetic logic unit (TALU) to multiply a block of elements of the first matrix with a block of elements of the second matrix to generate a product and to accumulate the product with a block of elements of the third matrix, wherein each lane is to multiply one or more different blocks of the first and second matrix and to accumulate the resulting one or more products with one or more different blocks of the third matrix; and broadcast circuitry to broadcast one or more invariant matrix blocks to different tile registers within a lane and/or different tile registers across different lanes.

公开(公告)号：US10534747B2

公开(公告)日：2020-01-14

申请号：US16368983

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram ,  Jawad B. Khan

IPC: G06F7/38 ,  H03K19/173 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

公开(公告)号：US20190272173A1

公开(公告)日：2019-09-05

申请号：US16419483

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram

IPC: G06F9/30 ,  G06F9/50

Abstract: Technologies for providing adaptive memory media management include media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry. The media access circuitry is further to manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.

公开(公告)号：US20190272121A1

公开(公告)日：2019-09-05

申请号：US16414265

申请日：2019-05-16

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram

IPC: G06F3/06 ,  H03M13/29 ,  G06F11/10 ,  G06N3/08 ,  G11C7/10

Abstract: Technologies for providing multiple tier memory media management include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory compute operation. Additionally, the media access circuitry is to read, in response to the request, data from a memory media region of the memory media, write the read data into a compute media region of the memory, perform, on the data in the compute media region, the in-memory compute operation, write, to the memory media region, resultant data indicative of a result of performance of the in-memory compute operation.

公开(公告)号：US20190227981A1

公开(公告)日：2019-07-25

申请号：US16368983

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram ,  Jawad B. Khan

IPC: G06F15/78 ,  G06F17/16 ,  G06F15/80

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.