公开(公告)号：US10006942B2

公开(公告)日：2018-06-26

申请号：US13892398

申请日：2013-05-13

Applicant: Intel IP Corporation

Inventor： Benjamin Orr ,  Harald Gossner

IPC: G01R31/02 ,  G01R1/073 ,  H05K1/11 ,  G01R31/00 ,  H05K1/14 ,  H05K1/02

CPC classification number: G01R1/07378 ,  G01R31/002 ,  H05K1/0268 ,  H05K1/11 ,  H05K1/144 ,  H05K2201/09227 ,  H05K2201/10378

Abstract: A board may include a first set of board contact pads arranged on a first side of the board, the pads configured to connect to circuit pads of a circuit under test, the positions of the pads matching to the positions of the circuit pads; a fan-out region on the first side of the board including fan-out contact pads configured to at least one of receive a test signal and provide a measurement signal; at least one contact pad connecting to at least one pad of the first set of board pads; and a second set of board contact pads on a second side of the board, the second set of board pads configured to connect to test board pads of a test board; positions of the pads matching to the positions of the test board pads; a pad connecting to a pad of the first set of board pads.

公开(公告)号：US09818672B2

公开(公告)日：2017-11-14

申请号：US14181325

申请日：2014-02-14

Applicant: INTEL IP CORPORATION

Inventor： Michael P. Skinner ,  Sven Albers ,  Harald Gossner ,  Peter Baumgartner ,  Hans-Joachim Barth

IPC: H01L23/467 ,  H01L23/473

CPC classification number: H01L23/467 ,  H01L23/473 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Embodiments of flow diversion devices (FDDs) are disclosed herein. An FDD may include a body formed of a body material and a plurality of thermally deformable fins arranged along the body. Individual fins of the plurality of fins may include first and second materials having different coefficients of thermal expansion (CTEs). Other embodiments may be disclosed and/or claimed.

公开(公告)号：US09209143B2

公开(公告)日：2015-12-08

申请号：US14038248

申请日：2013-09-26

Applicant: Intel IP Corporation

Inventor： Georg Seidemann ,  Sven Albers ,  Teodora Ossiander ,  Michael Skinner ,  Hans-Joachim Barth ,  Harald Gossner ,  Reinhard Mahnkopf ,  Christian Mueller ,  Wolfgang Molzer

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05016 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06135 ,  H01L2224/06155 ,  H01L2224/06183 ,  H01L2224/08054 ,  H01L2224/08056 ,  H01L2224/08057 ,  H01L2224/08121 ,  H01L2224/08137 ,  H01L2224/08225 ,  H01L2224/09135 ,  H01L2224/09183 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/16137 ,  H01L2224/48137 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/81203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, a second IC die including a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, wherein the second IC die is arranged adjacent to the first IC die, and includes an electrically conductive bond in contact with at least one of the top surface or the side surface of the multi-surface contact pad of the first IC die and the top surface of the multi-surface contact pad of the second IC die.

Abstract translation: 一种装置包括第一集成电路（IC）芯片，其包括顶层，底表面，从顶层的顶表面延伸到底表面的侧壁表面，以及至少一个多表面接触垫，第二 IC芯片包括顶层，底面，从顶层的顶表面延伸到底表面的侧壁表面，以及至少一个多表面接触焊盘，其中第二IC管芯被布置为与第一IC 并且包括与第一IC管芯的多表面接触焊盘的顶表面或侧表面中的至少一个与第二IC管芯的多表面接触焊盘的顶表面接触的导电接合 。

公开(公告)号：US11355924B2

公开(公告)日：2022-06-07

申请号：US16976083

申请日：2019-05-22

Applicant: Intel IP Corporation

Inventor： Krzysztof Domanski ,  David Johnsson ,  Harald Gossner ,  Jenia Elkind

IPC: H02H9/02 ,  H01L27/02 ,  H02H9/04 ,  H03H11/04

Abstract: A circuit for electrostatic discharge (ESD) protection for wide frequency range multi-band interfaces. The interface may be split into a plurality of signal paths. Each signal path may include an ESD protection circuit configured to shunt an ESD current on each signal path to either ground or supply voltage and a filter configured to block signals from other signal paths. The signal paths are connected to a common signal line such that the signals for the plurality of signal paths can be transported simultaneously. The plurality of signal paths may be a high frequency path and a low frequency path. The low frequency path may include an inductor connected in series and the high frequency path may include a capacitor or transformer connected in series. The ESD protection circuit on each signal path is placed behind the inductor, the capacitor or the transformer.

公开(公告)号：US10082534B2

公开(公告)日：2018-09-25

申请号：US15029066

申请日：2015-06-17

Applicant: Intel IP Corporation

Inventor： Harald Gossner ,  Krzysztof Domanski ,  David Johnsson ,  Benjamin J. Orr

IPC: G01R31/28 ,  G01R31/304 ,  G01R31/306 ,  G01R31/309 ,  G01R31/14

CPC classification number: G01R31/281 ,  G01R31/002 ,  G01R31/14 ,  G01R31/2851 ,  G01R31/2879

Abstract: A directional pulse injection system and method are described for injecting a pulse into a microelectronic system for electrostatic test. One example has a transformer coupled to a pulse source through a transmission line and to a conductive trace of a test board to apply the electrical pulse to the trace as a test pulse. The test board is connected to a microelectronic device under test. This example also has a cancellation pulse transmission line coupled to the pulse source and a cancellation pulse contact coupled to the pulse source through the cancellation pulse transmission line and to the trace on a side of the trace opposite the transformer to receive a cancellation signal from the pulse source and to couple the cancellation signal to the trace to cancel a portion of the test pulse.