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公开(公告)号:US09773725B2
公开(公告)日:2017-09-26
申请号:US14613893
申请日:2015-02-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
CPC classification number: H01L23/49822 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L24/16 , H01L2224/16 , H01L2224/16235 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/3011 , H05K1/0231 , H05K1/024 , H05K1/0251 , H05K1/113 , H05K1/144 , H05K2201/0187 , H05K2201/041 , H05K2201/09481 , H05K2201/09718 , H05K2201/10734 , Y10T29/49124 , Y10T29/49151 , H01L2924/00
Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
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公开(公告)号:US20170006709A1
公开(公告)日:2017-01-05
申请号:US14859382
申请日:2015-09-21
Applicant: International Business Machines Corporation
Inventor: Zhaoqing Chen , Matteo Cocchini , Rohan Mandrekar , Tingdong Zhou
IPC: H05K3/30
CPC classification number: G06F17/5072 , G06F2217/82 , H01G4/06 , H01G4/224 , H01G13/00 , H05K1/0231 , H05K1/162
Abstract: In one embodiment, a method includes positioning a first signal pad in a first layer of a printed circuit board and positioning a second signal pad in a second layer of the printed circuit board. The second signal pad is positioned to form an embedded capacitance between the first signal pad and the second signal pad. The embedded capacitance between the first signal pad and the second signal pad is configured to carry a signal between the first layer and the second layer absent a signal via.
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公开(公告)号:US20160225705A1
公开(公告)日:2016-08-04
申请号:US14613893
申请日:2015-02-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
IPC: H01L23/498 , H05K1/14
CPC classification number: H01L23/49822 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L24/16 , H01L2224/16 , H01L2224/16235 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/3011 , H05K1/0231 , H05K1/024 , H05K1/0251 , H05K1/113 , H05K1/144 , H05K2201/0187 , H05K2201/041 , H05K2201/09481 , H05K2201/09718 , H05K2201/10734 , Y10T29/49124 , Y10T29/49151 , H01L2924/00
Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
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